<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP3C120/EP4CE115 (0x020F70DD)" sof_file="" top_level_entity="DE2_115_ADDA">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <position_info>
      <single attribute="active tab" value="0"/>
      <single attribute="data horizontal scroll position" value="90"/>
      <single attribute="data vertical scroll position" value="0"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom level numerator" value="16"/>
      <single attribute="zoom offset denominator" value="1"/>
      <single attribute="zoom offset numerator" value="8064"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2010/07/21 13:24:43  #0">
      <clock name="DE2_115_ADDA_TOP:U1|pll:pll_100|c0" polarity="posedge" tap_mode="classic"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="ADC_DB[0]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[10]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[11]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[12]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[13]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[1]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[2]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[3]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[4]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[5]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[6]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[7]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[8]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[9]" tap_mode="classic" type="input pin"/>
          <wire name="DAC_DA[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[10]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[11]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[12]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[13]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[7]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[8]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[9]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[10]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[11]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[12]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[13]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[7]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[8]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[9]" tap_mode="classic" type="output pin"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[9]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[9]" tap_mode="classic" type="combinatorial"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="ADC_DB[0]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[10]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[11]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[12]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[13]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[1]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[2]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[3]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[4]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[5]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[6]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[7]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[8]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[9]" tap_mode="classic" type="input pin"/>
          <wire name="DAC_DA[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[10]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[11]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[12]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[13]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[7]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[8]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[9]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[10]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[11]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[12]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[13]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[7]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[8]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[9]" tap_mode="classic" type="output pin"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[9]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[9]" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
        <storage_qualifier_input_vec>
          <wire name="ADC_DB[0]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[10]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[11]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[12]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[13]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[1]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[2]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[3]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[4]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[5]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[6]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[7]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[8]" tap_mode="classic" type="input pin"/>
          <wire name="ADC_DB[9]" tap_mode="classic" type="input pin"/>
          <wire name="DAC_DA[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[10]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[11]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[12]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[13]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[7]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[8]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DA[9]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[0]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[10]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[11]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[12]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[13]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[1]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[2]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[3]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[4]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[5]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[6]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[7]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[8]" tap_mode="classic" type="output pin"/>
          <wire name="DAC_DB[9]" tap_mode="classic" type="output pin"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[9]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[9]" tap_mode="classic" type="combinatorial"/>
        </storage_qualifier_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="DAC_DA" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAC_DA[0]"/>
            <net is_signal_inverted="no" name="DAC_DA[1]"/>
            <net is_signal_inverted="no" name="DAC_DA[2]"/>
            <net is_signal_inverted="no" name="DAC_DA[3]"/>
            <net is_signal_inverted="no" name="DAC_DA[4]"/>
            <net is_signal_inverted="no" name="DAC_DA[5]"/>
            <net is_signal_inverted="no" name="DAC_DA[6]"/>
            <net is_signal_inverted="no" name="DAC_DA[7]"/>
            <net is_signal_inverted="no" name="DAC_DA[8]"/>
            <net is_signal_inverted="no" name="DAC_DA[9]"/>
            <net is_signal_inverted="no" name="DAC_DA[10]"/>
            <net is_signal_inverted="no" name="DAC_DA[11]"/>
            <net is_signal_inverted="no" name="DAC_DA[12]"/>
            <net is_signal_inverted="no" name="DAC_DA[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DAC_DB" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAC_DB[0]"/>
            <net is_signal_inverted="no" name="DAC_DB[1]"/>
            <net is_signal_inverted="no" name="DAC_DB[2]"/>
            <net is_signal_inverted="no" name="DAC_DB[3]"/>
            <net is_signal_inverted="no" name="DAC_DB[4]"/>
            <net is_signal_inverted="no" name="DAC_DB[5]"/>
            <net is_signal_inverted="no" name="DAC_DB[6]"/>
            <net is_signal_inverted="no" name="DAC_DB[7]"/>
            <net is_signal_inverted="no" name="DAC_DB[8]"/>
            <net is_signal_inverted="no" name="DAC_DB[9]"/>
            <net is_signal_inverted="no" name="DAC_DB[10]"/>
            <net is_signal_inverted="no" name="DAC_DB[11]"/>
            <net is_signal_inverted="no" name="DAC_DB[12]"/>
            <net is_signal_inverted="no" name="DAC_DB[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="ADC_DB" order="lsb_to_msb" radix="line" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="ADC_DB[0]"/>
            <net is_signal_inverted="no" name="ADC_DB[1]"/>
            <net is_signal_inverted="no" name="ADC_DB[2]"/>
            <net is_signal_inverted="no" name="ADC_DB[3]"/>
            <net is_signal_inverted="no" name="ADC_DB[4]"/>
            <net is_signal_inverted="no" name="ADC_DB[5]"/>
            <net is_signal_inverted="no" name="ADC_DB[6]"/>
            <net is_signal_inverted="no" name="ADC_DB[7]"/>
            <net is_signal_inverted="no" name="ADC_DB[8]"/>
            <net is_signal_inverted="no" name="ADC_DB[9]"/>
            <net is_signal_inverted="no" name="ADC_DB[10]"/>
            <net is_signal_inverted="no" name="ADC_DB[11]"/>
            <net is_signal_inverted="no" name="ADC_DB[12]"/>
            <net is_signal_inverted="no" name="ADC_DB[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa" order="lsb_to_msb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[0]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[1]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[2]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[3]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[4]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[5]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[6]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[7]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[8]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[9]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[10]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[11]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[12]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab" order="lsb_to_msb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[0]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[1]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[2]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[3]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[4]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[5]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[6]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[7]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[8]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[9]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[10]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[11]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[12]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[13]"/>
          </bus>
        </data_view>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="ADC_DB" order="lsb_to_msb" radix="line" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="ADC_DB[0]"/>
            <net is_signal_inverted="no" name="ADC_DB[1]"/>
            <net is_signal_inverted="no" name="ADC_DB[2]"/>
            <net is_signal_inverted="no" name="ADC_DB[3]"/>
            <net is_signal_inverted="no" name="ADC_DB[4]"/>
            <net is_signal_inverted="no" name="ADC_DB[5]"/>
            <net is_signal_inverted="no" name="ADC_DB[6]"/>
            <net is_signal_inverted="no" name="ADC_DB[7]"/>
            <net is_signal_inverted="no" name="ADC_DB[8]"/>
            <net is_signal_inverted="no" name="ADC_DB[9]"/>
            <net is_signal_inverted="no" name="ADC_DB[10]"/>
            <net is_signal_inverted="no" name="ADC_DB[11]"/>
            <net is_signal_inverted="no" name="ADC_DB[12]"/>
            <net is_signal_inverted="no" name="ADC_DB[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DAC_DA" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAC_DA[0]"/>
            <net is_signal_inverted="no" name="DAC_DA[1]"/>
            <net is_signal_inverted="no" name="DAC_DA[2]"/>
            <net is_signal_inverted="no" name="DAC_DA[3]"/>
            <net is_signal_inverted="no" name="DAC_DA[4]"/>
            <net is_signal_inverted="no" name="DAC_DA[5]"/>
            <net is_signal_inverted="no" name="DAC_DA[6]"/>
            <net is_signal_inverted="no" name="DAC_DA[7]"/>
            <net is_signal_inverted="no" name="DAC_DA[8]"/>
            <net is_signal_inverted="no" name="DAC_DA[9]"/>
            <net is_signal_inverted="no" name="DAC_DA[10]"/>
            <net is_signal_inverted="no" name="DAC_DA[11]"/>
            <net is_signal_inverted="no" name="DAC_DA[12]"/>
            <net is_signal_inverted="no" name="DAC_DA[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DAC_DB" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAC_DB[0]"/>
            <net is_signal_inverted="no" name="DAC_DB[1]"/>
            <net is_signal_inverted="no" name="DAC_DB[2]"/>
            <net is_signal_inverted="no" name="DAC_DB[3]"/>
            <net is_signal_inverted="no" name="DAC_DB[4]"/>
            <net is_signal_inverted="no" name="DAC_DB[5]"/>
            <net is_signal_inverted="no" name="DAC_DB[6]"/>
            <net is_signal_inverted="no" name="DAC_DB[7]"/>
            <net is_signal_inverted="no" name="DAC_DB[8]"/>
            <net is_signal_inverted="no" name="DAC_DB[9]"/>
            <net is_signal_inverted="no" name="DAC_DB[10]"/>
            <net is_signal_inverted="no" name="DAC_DB[11]"/>
            <net is_signal_inverted="no" name="DAC_DB[12]"/>
            <net is_signal_inverted="no" name="DAC_DB[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa" order="lsb_to_msb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[0]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[1]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[2]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[3]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[4]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[5]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[6]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[7]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[8]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[9]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[10]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[11]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[12]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|dataa[13]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab" order="lsb_to_msb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[0]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[1]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[2]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[3]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[4]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[5]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[6]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[7]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[8]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[9]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[10]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[11]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[12]"/>
            <net is_signal_inverted="no" name="DE2_115_ADDA_TOP:U1|lpm_add:lpm|datab[13]"/>
          </bus>
        </setup_view>
      </presentation>
      <trigger CRC="E3DB75C6" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2010/07/21 13:24:43  #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
        <events use_custom_flow_control="no">
          <level enabled="yes" name="condition1" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
        </events>
        <storage_qualifier_events>
          <transitional>0000000000000000000000000000000000000000000000000000000000000000000000
            <pwr_up_transitional>0000000000000000000000000000000000000000000000000000000000000000000000
            </pwr_up_transitional>
          </transitional>
          <storage_qualifier_level type="basic">
            <power_up>
            </power_up>
            <op_node/>
          </storage_qualifier_level>
          <storage_qualifier_level type="basic">
            <power_up>
            </power_up>
            <op_node/>
          </storage_qualifier_level>
          <storage_qualifier_level type="basic">
            <power_up>
            </power_up>
            <op_node/>
          </storage_qualifier_level>
        </storage_qualifier_events>
        <log>
          <data global_temp="1" name="log: 2010/07/21 13:27:16  #0" power_up_mode="false" sample_depth="2047" trigger_position="256">[encoded data, 143360 characters]</data>
          <extradata>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>
        </log>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
  <static_plugin_mnemonics/>
  <global_info>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
    <multi attribute="window position" size="9" value="1600,805,398,124,0,50,124,0,0"/>
  </global_info>
</session>
