TimeQuest Timing Analyzer report for DE2_115_ADDA
Fri Jun 17 21:14:41 2011
Quartus II Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'U1|pll_100|altpll_component|pll|clk[0]'
 13. Slow 1200mV 85C Model Setup: 'altera_reserved_tck'
 14. Slow 1200mV 85C Model Hold: 'U1|pll_100|altpll_component|pll|clk[0]'
 15. Slow 1200mV 85C Model Hold: 'altera_reserved_tck'
 16. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'
 17. Slow 1200mV 85C Model Removal: 'altera_reserved_tck'
 18. Slow 1200mV 85C Model Minimum Pulse Width: 'U1|pll_100|altpll_component|pll|clk[0]'
 19. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
 20. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK2_50'
 21. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK3_50'
 22. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'
 23. Setup Times
 24. Hold Times
 25. Clock to Output Times
 26. Minimum Clock to Output Times
 27. Slow 1200mV 85C Model Metastability Report
 28. Slow 1200mV 0C Model Fmax Summary
 29. Slow 1200mV 0C Model Setup Summary
 30. Slow 1200mV 0C Model Hold Summary
 31. Slow 1200mV 0C Model Recovery Summary
 32. Slow 1200mV 0C Model Removal Summary
 33. Slow 1200mV 0C Model Minimum Pulse Width Summary
 34. Slow 1200mV 0C Model Setup: 'U1|pll_100|altpll_component|pll|clk[0]'
 35. Slow 1200mV 0C Model Setup: 'altera_reserved_tck'
 36. Slow 1200mV 0C Model Hold: 'altera_reserved_tck'
 37. Slow 1200mV 0C Model Hold: 'U1|pll_100|altpll_component|pll|clk[0]'
 38. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'
 39. Slow 1200mV 0C Model Removal: 'altera_reserved_tck'
 40. Slow 1200mV 0C Model Minimum Pulse Width: 'U1|pll_100|altpll_component|pll|clk[0]'
 41. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
 42. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50'
 43. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50'
 44. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
 45. Setup Times
 46. Hold Times
 47. Clock to Output Times
 48. Minimum Clock to Output Times
 49. Slow 1200mV 0C Model Metastability Report
 50. Fast 1200mV 0C Model Setup Summary
 51. Fast 1200mV 0C Model Hold Summary
 52. Fast 1200mV 0C Model Recovery Summary
 53. Fast 1200mV 0C Model Removal Summary
 54. Fast 1200mV 0C Model Minimum Pulse Width Summary
 55. Fast 1200mV 0C Model Setup: 'U1|pll_100|altpll_component|pll|clk[0]'
 56. Fast 1200mV 0C Model Setup: 'altera_reserved_tck'
 57. Fast 1200mV 0C Model Hold: 'U1|pll_100|altpll_component|pll|clk[0]'
 58. Fast 1200mV 0C Model Hold: 'altera_reserved_tck'
 59. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'
 60. Fast 1200mV 0C Model Removal: 'altera_reserved_tck'
 61. Fast 1200mV 0C Model Minimum Pulse Width: 'U1|pll_100|altpll_component|pll|clk[0]'
 62. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
 63. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50'
 64. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50'
 65. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
 66. Setup Times
 67. Hold Times
 68. Clock to Output Times
 69. Minimum Clock to Output Times
 70. Fast 1200mV 0C Model Metastability Report
 71. Multicorner Timing Analysis Summary
 72. Setup Times
 73. Hold Times
 74. Clock to Output Times
 75. Minimum Clock to Output Times
 76. Board Trace Model Assignments
 77. Input Transition Times
 78. Signal Integrity Metrics (Slow 1200mv 0c Model)
 79. Signal Integrity Metrics (Slow 1200mv 85c Model)
 80. Signal Integrity Metrics (Fast 1200mv 0c Model)
 81. Setup Transfers
 82. Hold Transfers
 83. Recovery Transfers
 84. Removal Transfers
 85. Report TCCS
 86. Report RSKM
 87. Unconstrained Paths
 88. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition ;
; Revision Name      ; DE2_115_ADDA                                                    ;
; Device Family      ; Cyclone IV E                                                    ;
; Device Name        ; EP4CE115F29C8                                                   ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Enabled                                                         ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; DE2_115_ADDA.SDC ; OK     ; Fri Jun 17 21:14:22 2011 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                   ;
+----------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------+--------------------------------------------+
; Clock Name                             ; Type      ; Period  ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                   ; Targets                                    ;
+----------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------+--------------------------------------------+
; altera_reserved_tck                    ; Base      ; 100.000 ; 10.0 MHz  ; 0.000 ; 50.000 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                          ; { altera_reserved_tck }                    ;
; CLOCK2_50                              ; Base      ; 20.000  ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                          ; { CLOCK2_50 }                              ;
; CLOCK3_50                              ; Base      ; 20.000  ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                          ; { CLOCK3_50 }                              ;
; CLOCK_50                               ; Base      ; 20.000  ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                          ; { CLOCK_50 }                               ;
; U1|pll_100|altpll_component|pll|clk[0] ; Generated ; 8.000   ; 125.0 MHz ; 0.000 ; 4.000  ; 50.00      ; 2         ; 5           ;       ;        ;           ;            ; false    ; CLOCK_50 ; U1|pll_100|altpll_component|pll|inclk[0] ; { U1|pll_100|altpll_component|pll|clk[0] } ;
; U1|pll_100|altpll_component|pll|clk[1] ; Generated ; 16.000  ; 62.5 MHz  ; 0.000 ; 8.000  ; 50.00      ; 4         ; 5           ;       ;        ;           ;            ; false    ; CLOCK_50 ; U1|pll_100|altpll_component|pll|inclk[0] ; { U1|pll_100|altpll_component|pll|clk[1] } ;
+----------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------+--------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                            ;
+------------+-----------------+----------------------------------------+-------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                             ; Note                                                  ;
+------------+-----------------+----------------------------------------+-------------------------------------------------------+
; 81.97 MHz  ; 24.21 MHz       ; altera_reserved_tck                    ; limit due to high minimum pulse width violation (tch) ;
; 186.99 MHz ; 186.99 MHz      ; U1|pll_100|altpll_component|pll|clk[0] ;                                                       ;
+------------+-----------------+----------------------------------------+-------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                             ;
+----------------------------------------+--------+---------------+
; Clock                                  ; Slack  ; End Point TNS ;
+----------------------------------------+--------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 2.652  ; 0.000         ;
; altera_reserved_tck                    ; 43.900 ; 0.000         ;
+----------------------------------------+--------+---------------+


+----------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                             ;
+----------------------------------------+-------+---------------+
; Clock                                  ; Slack ; End Point TNS ;
+----------------------------------------+-------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 0.393 ; 0.000         ;
; altera_reserved_tck                    ; 0.441 ; 0.000         ;
+----------------------------------------+-------+---------------+


+----------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary       ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 43.466 ; 0.000         ;
+---------------------+--------+---------------+


+----------------------------------------------+
; Slow 1200mV 85C Model Removal Summary        ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; -2.424 ; -2.424        ;
+---------------------+--------+---------------+


+-----------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary               ;
+----------------------------------------+--------+---------------+
; Clock                                  ; Slack  ; End Point TNS ;
+----------------------------------------+--------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 3.000  ; 0.000         ;
; CLOCK_50                               ; 9.891  ; 0.000         ;
; CLOCK2_50                              ; 16.000 ; 0.000         ;
; CLOCK3_50                              ; 16.000 ; 0.000         ;
; altera_reserved_tck                    ; 29.350 ; 0.000         ;
+----------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                                                                 ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                             ; To Node                                                                                                                    ; Launch Clock                           ; Latch Clock                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; 2.652 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 5.275      ;
; 2.671 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 5.256      ;
; 2.721 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 5.206      ;
; 2.739 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 5.188      ;
; 2.749 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.093     ; 5.159      ;
; 2.810 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.104     ; 5.087      ;
; 2.835 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][7]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 5.092      ;
; 2.855 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][2]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.117     ; 5.029      ;
; 2.866 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 5.049      ;
; 2.866 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.132     ; 5.003      ;
; 2.896 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][1]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.103     ; 5.002      ;
; 2.896 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.978      ;
; 2.896 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.978      ;
; 2.896 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.978      ;
; 2.896 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.978      ;
; 2.898 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.976      ;
; 2.898 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.976      ;
; 2.898 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.976      ;
; 2.898 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.976      ;
; 2.898 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.127     ; 4.976      ;
; 2.898 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][6]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.117     ; 4.986      ;
; 2.900 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 5.015      ;
; 2.901 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 5.026      ;
; 2.907 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.103     ; 4.991      ;
; 2.911 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.080     ; 5.010      ;
; 2.913 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.966      ;
; 2.913 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.966      ;
; 2.913 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.966      ;
; 2.921 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.083     ; 4.997      ;
; 2.925 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.093     ; 4.983      ;
; 2.937 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][23]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.093     ; 4.971      ;
; 2.939 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][0]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.117     ; 4.945      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][2]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.941 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][1]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.937      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][2]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.959 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][1]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.123     ; 4.919      ;
; 2.967 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.104     ; 4.930      ;
; 2.967 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][4]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.117     ; 4.917      ;
; 2.968 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][0]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][23]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.103     ; 4.930      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[15]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[14]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[13]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[12]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[11]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[10]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[0]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[7]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[6]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[5]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[4]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[3]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[2]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[1]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.970 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[16]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.130     ; 4.901      ;
; 2.979 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n|pipe[0][9]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][20] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.091     ; 4.931      ;
; 2.982 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][0]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.103     ; 4.916      ;
; 2.984 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_5_n|pipe[0][10]            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][19] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 4.931      ;
; 2.991 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][9]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 4.936      ;
; 2.992 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 4.923      ;
; 3.001 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][18]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.003 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.122     ; 4.876      ;
; 3.008 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][3]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.103     ; 4.890      ;
; 3.008 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][3]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.117     ; 4.876      ;
; 3.010 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][33]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.108     ; 4.883      ;
; 3.011 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][7]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.103     ; 4.887      ;
; 3.022 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][11]            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 4.893      ;
; 3.022 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][32]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.108     ; 4.871      ;
; 3.027 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][1]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.117     ; 4.857      ;
; 3.028 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 4.887      ;
; 3.030 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][4]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.095     ; 4.876      ;
; 3.031 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][15]            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.077     ; 4.893      ;
; 3.035 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.093     ; 4.873      ;
; 3.035 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][9]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.080     ; 4.886      ;
; 3.038 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_1_n|pipe[0][7]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.091     ; 4.872      ;
; 3.040 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_3_n_0_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][33]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.092     ; 4.869      ;
; 3.040 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.086     ; 4.875      ;
; 3.041 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][3]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.102     ; 4.858      ;
; 3.045 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][8]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 4.882      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                ; To Node                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 43.900 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.098     ; 6.003      ;
; 44.230 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.941      ; 8.712      ;
; 44.230 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.941      ; 8.712      ;
; 44.230 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.941      ; 8.712      ;
; 44.230 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.941      ; 8.712      ;
; 44.230 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.941      ; 8.712      ;
; 44.503 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.442      ;
; 44.517 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.428      ;
; 44.518 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.427      ;
; 44.522 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.423      ;
; 44.545 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.943      ; 8.399      ;
; 44.569 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.943      ; 8.375      ;
; 44.680 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.265      ;
; 44.685 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.260      ;
; 44.708 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.237      ;
; 44.709 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.944      ; 8.236      ;
; 44.759 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.943      ; 8.185      ;
; 44.794 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.943      ; 8.150      ;
; 45.002 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.942      ; 7.941      ;
; 45.002 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.942      ; 7.941      ;
; 45.002 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.942      ; 7.941      ;
; 45.002 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.942      ; 7.941      ;
; 45.389 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.239     ; 4.373      ;
; 45.533 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.098     ; 4.370      ;
; 45.535 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.943      ; 7.409      ;
; 45.792 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.528      ; 4.737      ;
; 45.896 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0] ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.241     ; 3.864      ;
; 46.561 ; sld_hub:auto_hub|irsr_reg[1]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.519      ; 3.959      ;
; 46.589 ; sld_hub:auto_hub|irsr_reg[0]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.519      ; 3.931      ;
; 46.644 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.241     ; 3.116      ;
; 46.923 ; sld_hub:auto_hub|irsr_reg[2]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.519      ; 3.597      ;
; 47.040 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.520      ; 3.481      ;
; 47.853 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.521      ; 2.669      ;
; 47.887 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.521      ; 2.635      ;
; 48.302 ; sld_hub:auto_hub|tdo_bypass_reg                                          ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.521      ; 2.220      ;
; 48.804 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.527      ; 1.724      ;
; 94.272 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 5.640      ;
; 94.505 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.120     ; 3.376      ;
; 94.505 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.120     ; 3.376      ;
; 94.505 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.120     ; 3.376      ;
; 94.505 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.120     ; 3.376      ;
; 94.505 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.120     ; 3.376      ;
; 94.731 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 5.180      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.740 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.119     ; 3.142      ;
; 94.896 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.083     ; 5.022      ;
; 94.985 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.928      ;
; 94.985 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.928      ;
; 94.985 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.928      ;
; 94.985 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.928      ;
; 95.001 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 4.918      ;
; 95.189 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[15]                     ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.100     ; 4.712      ;
; 95.305 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.915     ; 2.781      ;
; 95.315 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.598      ;
; 95.315 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.598      ;
; 95.315 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[2]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.598      ;
; 95.331 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.582      ;
; 95.331 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.582      ;
; 95.331 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.582      ;
; 95.331 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.582      ;
; 95.352 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 4.569      ;
; 95.352 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 4.569      ;
; 95.352 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[2]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 4.569      ;
; 95.390 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.530      ;
; 95.405 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.915     ; 2.681      ;
; 95.484 ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.096     ; 4.421      ;
; 95.484 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.436      ;
; 95.520 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.392      ;
; 95.522 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.391      ;
; 95.522 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.391      ;
; 95.522 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.391      ;
; 95.522 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.391      ;
; 95.526 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.772     ; 2.703      ;
; 95.526 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.772     ; 2.703      ;
; 95.526 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.772     ; 2.703      ;
; 95.526 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.772     ; 2.703      ;
; 95.526 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.772     ; 2.703      ;
; 95.533 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.915     ; 2.553      ;
; 95.615 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|hub_mode_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 4.298      ;
; 95.617 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.303      ;
; 95.617 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.303      ;
; 95.617 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.303      ;
; 95.617 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.303      ;
; 95.659 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.771     ; 2.571      ;
; 95.659 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.771     ; 2.571      ;
; 95.659 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.771     ; 2.571      ;
; 95.659 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.771     ; 2.571      ;
; 95.741 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.097     ; 4.163      ;
; 95.741 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.097     ; 4.163      ;
; 95.741 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.097     ; 4.163      ;
; 95.741 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.097     ; 4.163      ;
; 95.741 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.097     ; 4.163      ;
; 95.748 ; sld_hub:auto_hub|irf_reg[1][1]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.915     ; 2.338      ;
; 95.755 ; sld_hub:auto_hub|irf_reg[1][1]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.915     ; 2.331      ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                ; Launch Clock                           ; Latch Clock                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; 0.393 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[6]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.138      ;
; 0.397 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[8]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.142      ;
; 0.403 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[2]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.148      ;
; 0.404 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[6]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.140      ;
; 0.408 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[10]                                                                                    ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.153      ;
; 0.415 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[7]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.160      ;
; 0.421 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[1]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.166      ;
; 0.421 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[4]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.166      ;
; 0.422 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[0]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.167      ;
; 0.422 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[3]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.523      ; 1.199      ;
; 0.422 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[3]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.524      ; 1.200      ;
; 0.426 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[6]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.483      ; 1.163      ;
; 0.426 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[5]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.162      ;
; 0.429 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[11]                                                                                    ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.174      ;
; 0.429 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[4]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.523      ; 1.206      ;
; 0.429 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[4]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.524      ; 1.207      ;
; 0.430 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[3]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.166      ;
; 0.432 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[12]                                                                                    ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.177      ;
; 0.433 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[9]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.178      ;
; 0.433 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[1]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.523      ; 1.210      ;
; 0.433 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[1]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.524      ; 1.211      ;
; 0.435 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cs[7]                                                                                                                            ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.171      ;
; 0.436 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[5]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.181      ;
; 0.439 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[7]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.483      ; 1.176      ;
; 0.442 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.746      ;
; 0.442 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[0] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[0]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.746      ;
; 0.442 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[1] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[1]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.746      ;
; 0.442 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[2] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[2]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.746      ;
; 0.442 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|was_stalled                                                                                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|was_stalled                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.746      ;
; 0.443 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|empty_dff       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|empty_dff                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.746      ;
; 0.443 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|usedw_is_0_dff  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|usedw_is_0_dff                                         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.746      ;
; 0.443 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[2]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[2]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.746      ;
; 0.443 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[3]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[3]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.746      ;
; 0.443 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.746      ;
; 0.443 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.746      ;
; 0.444 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[2]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.180      ;
; 0.448 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[0]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.184      ;
; 0.454 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|rd_ptr_lsb      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|rd_ptr_lsb                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.758      ;
; 0.456 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[3]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.491      ; 1.201      ;
; 0.456 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated|pipeline_dffe[0]                                                                          ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated|pipeline_dffe[0]                                                                                                                 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.090      ; 0.758      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[5]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.523      ; 1.236      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[5]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.524      ; 1.237      ;
; 0.477 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[4]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.213      ;
; 0.479 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[6]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.215      ;
; 0.480 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_ready_s                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.784      ;
; 0.481 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002|dxxpdo[20]                                                                                                                                  ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[7]                                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.784      ;
; 0.483 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002|dxxpdo[19]                                                                                                                                  ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[6]                                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.786      ;
; 0.484 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[1]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.482      ; 1.220      ;
; 0.484 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.787      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n|pipe[0][8]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_8_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_10_pp|data_out[0]                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_5_n|pipe[0][10]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[14]                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[0]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.792      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][12]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][12]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_2_n|pipe[0][8]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_1_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][2]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][2]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][2]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][2]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][23]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][23]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.489 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_6_n|pipe[0][13]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_3_n|pipe[0][13]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[5]                                                                                                                               ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[6]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[1]                                                                                                                               ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[2]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[0]                                                                                                                               ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[1]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[2]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.523      ; 1.267      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[2]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.524      ; 1.268      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][20]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][20]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[7]                                                                                                  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[7]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[9]                                                                                                  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[9]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[4]                                                                                                  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[4]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][7]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][7]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][3]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][3]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_10_pp|data_out[0]                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_5_n|pipe[0][10]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.093      ; 0.795      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][1]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][1]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][0]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_8_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][2]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][2]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][1]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][1]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][32]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][32]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][21]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|data_int[0]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_2_n|pipe[0][9]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_1_n|pipe[0][9]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_6_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_4_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_2_n|pipe[0][4]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.794      ;
; 0.490 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.793      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][18]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][18]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.795      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[12]                                                                                                 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[12]                                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.795      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_6_n|pipe[0][13]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][13]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.795      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_6_n|pipe[0][12]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_3_n|pipe[0][12]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_6_n|pipe[0][12]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][12]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.795      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][9]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_1_n|pipe[0][9]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][8]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_1_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.092      ; 0.795      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_6_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[24]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[24]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[14]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[14]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[19]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[19]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[22]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[22]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[23]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[23]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
; 0.491 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][31]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][31]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.091      ; 0.794      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                  ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                 ; To Node                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.441 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.400      ; 3.053      ;
; 0.446 ; sld_hub:auto_hub|tdo                                                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 0.746      ;
; 0.493 ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 0.794      ;
; 0.500 ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 0.801      ;
; 0.501 ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 0.802      ;
; 0.502 ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 0.803      ;
; 0.628 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.399      ; 3.239      ;
; 0.628 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.399      ; 3.239      ;
; 0.628 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.399      ; 3.239      ;
; 0.628 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.399      ; 3.239      ;
; 0.628 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.399      ; 3.239      ;
; 0.691 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 0.993      ;
; 0.691 ; sld_hub:auto_hub|jtag_ir_reg[9]                                           ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 0.992      ;
; 0.692 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 0.994      ;
; 0.692 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 0.994      ;
; 0.698 ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 0.999      ;
; 0.699 ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.000      ;
; 0.729 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.708      ; 1.649      ;
; 0.736 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.038      ;
; 0.889 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.191      ;
; 0.891 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.193      ;
; 0.891 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.193      ;
; 0.925 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.226      ;
; 0.934 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.235      ;
; 0.937 ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.238      ;
; 0.960 ; sld_hub:auto_hub|irf_reg[1][0]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.708      ; 1.880      ;
; 1.030 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.332      ;
; 1.031 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.333      ;
; 1.038 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[14]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.339      ;
; 1.071 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.374      ;
; 1.076 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.707      ; 1.995      ;
; 1.088 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.390      ;
; 1.089 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.391      ;
; 1.090 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.392      ;
; 1.091 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.393      ;
; 1.097 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.400      ;
; 1.117 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.420      ;
; 1.117 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.418      ;
; 1.120 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.423      ;
; 1.125 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.426      ;
; 1.126 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.428      ;
; 1.134 ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.435      ;
; 1.143 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.444      ;
; 1.148 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.449      ;
; 1.153 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|irf_reg[1][2]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.453      ;
; 1.185 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.486      ;
; 1.230 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.532      ;
; 1.236 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.537      ;
; 1.240 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.541      ;
; 1.244 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.545      ;
; 1.251 ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.553      ;
; 1.263 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.707      ; 2.182      ;
; 1.267 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.567      ;
; 1.267 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.567      ;
; 1.267 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.567      ;
; 1.267 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.567      ;
; 1.267 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.567      ;
; 1.273 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.707      ; 2.192      ;
; 1.281 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.581      ;
; 1.290 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.591      ;
; 1.295 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.598      ;
; 1.326 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.629      ;
; 1.337 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.638      ;
; 1.344 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|virtual_ir_scan_reg                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.645      ;
; 1.347 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|virtual_dr_scan_reg                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.648      ;
; 1.357 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.658      ;
; 1.370 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.671      ;
; 1.370 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.672      ;
; 1.376 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.677      ;
; 1.379 ; sld_hub:auto_hub|tdo_bypass_reg                                           ; sld_hub:auto_hub|tdo_bypass_reg                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.680      ;
; 1.379 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                       ; sld_hub:auto_hub|reset_ena_reg                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.084      ; 1.675      ;
; 1.385 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.688      ;
; 1.400 ; sld_hub:auto_hub|irf_reg[1][0]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.707      ; 2.319      ;
; 1.411 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.714      ;
; 1.411 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|irf_reg[1][1]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.711      ;
; 1.416 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.719      ;
; 1.427 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.856      ; 2.495      ;
; 1.427 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.856      ; 2.495      ;
; 1.427 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.856      ; 2.495      ;
; 1.427 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.856      ; 2.495      ;
; 1.430 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.733      ;
; 1.450 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.750      ;
; 1.485 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.787      ;
; 1.486 ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; sld_hub:auto_hub|irf_reg[1][0]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.787      ;
; 1.487 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.789      ;
; 1.506 ; sld_hub:auto_hub|irf_reg[1][2]                                            ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.807      ;
; 1.537 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                       ; sld_hub:auto_hub|irsr_reg[4]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.831      ;
; 1.541 ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; sld_hub:auto_hub|irf_reg[1][1]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.842      ;
; 1.542 ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; sld_hub:auto_hub|irf_reg[1][2]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.843      ;
; 1.545 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[6]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[6]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.846      ;
; 1.557 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.857      ;
; 1.564 ; sld_hub:auto_hub|irsr_reg[3]                                              ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.865      ;
; 1.581 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.855      ; 2.648      ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                           ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                                  ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 43.466 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.524      ; 14.059     ;
; 43.466 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.524      ; 14.059     ;
; 43.466 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.524      ; 14.059     ;
; 43.466 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.524      ; 14.059     ;
; 43.466 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.524      ; 14.059     ;
; 43.664 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.525      ; 13.862     ;
; 43.664 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.525      ; 13.862     ;
; 43.664 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.525      ; 13.862     ;
; 43.664 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.525      ; 13.862     ;
; 47.387 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.527      ; 10.141     ;
; 48.747 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]    ; sld_hub:auto_hub|tdo                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.521      ; 1.775      ;
; 89.469 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.780     ; 8.752      ;
; 89.469 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.780     ; 8.752      ;
; 89.469 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.780     ; 8.752      ;
; 89.469 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.780     ; 8.752      ;
; 89.469 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.780     ; 8.752      ;
; 89.711 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.779     ; 8.511      ;
; 89.711 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.779     ; 8.511      ;
; 89.711 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.779     ; 8.511      ;
; 89.711 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.779     ; 8.511      ;
; 93.082 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.524      ; 14.443     ;
; 93.082 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.524      ; 14.443     ;
; 93.082 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.524      ; 14.443     ;
; 93.082 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.524      ; 14.443     ;
; 93.082 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.524      ; 14.443     ;
; 93.324 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.525      ; 14.202     ;
; 93.324 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.525      ; 14.202     ;
; 93.324 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.525      ; 14.202     ;
; 93.324 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.525      ; 14.202     ;
; 97.454 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 2.458      ;
; 97.699 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.527      ; 9.829      ;
; 97.759 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[3]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.152      ;
; 97.788 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; sld_hub:auto_hub|hub_mode_reg[2]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.097     ; 2.116      ;
; 97.835 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[4]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.098     ; 2.068      ;
; 97.835 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.098     ; 2.068      ;
; 97.862 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 2.051      ;
; 97.889 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.091     ; 2.021      ;
; 98.014 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.897      ;
; 98.014 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.897      ;
; 98.014 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.897      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.135 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.776      ;
; 98.139 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.773      ;
; 98.139 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_dr_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.773      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[8]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[7]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[9]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[6]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[2]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[5]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[4]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.263 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[3]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.649      ;
; 98.348 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[0]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.564      ;
; 98.348 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[1]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.564      ;
; 98.348 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[2]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.564      ;
; 98.348 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[0]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 1.564      ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'altera_reserved_tck'                                                                                                                                                                            ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                                  ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; -2.424 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.789      ; 7.577      ;
; 1.120  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[0]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.421      ;
; 1.120  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[1]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.421      ;
; 1.120  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[2]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.421      ;
; 1.120  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[0]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.421      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[8]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[7]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[9]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[6]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[2]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[5]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[4]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.187  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[3]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.488      ;
; 1.349  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.650      ;
; 1.349  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_dr_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.089      ; 1.650      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.368  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 1.668      ;
; 1.488  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.790      ;
; 1.488  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.790      ;
; 1.488  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.790      ;
; 1.587  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.090      ; 1.889      ;
; 1.639  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.087      ; 1.938      ;
; 1.661  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; sld_hub:auto_hub|hub_mode_reg[2]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.953      ;
; 1.683  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[4]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.975      ;
; 1.683  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.975      ;
; 1.711  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.787      ; 11.710     ;
; 1.711  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.787      ; 11.710     ;
; 1.711  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.787      ; 11.710     ;
; 1.711  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.787      ; 11.710     ;
; 1.755  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[3]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.088      ; 2.055      ;
; 1.944  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.786      ; 11.942     ;
; 1.944  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.786      ; 11.942     ;
; 1.944  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.786      ; 11.942     ;
; 1.944  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.786      ; 11.942     ;
; 1.944  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.786      ; 11.942     ;
; 1.988  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 2.291      ;
; 6.702  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.848      ; 7.762      ;
; 6.702  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.848      ; 7.762      ;
; 6.702  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.848      ; 7.762      ;
; 6.702  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.848      ; 7.762      ;
; 6.892  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.847      ; 7.951      ;
; 6.892  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.847      ; 7.951      ;
; 6.892  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.847      ; 7.951      ;
; 6.892  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.847      ; 7.951      ;
; 6.892  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.847      ; 7.951      ;
; 47.855 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.789      ; 7.876      ;
; 50.703 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]    ; sld_hub:auto_hub|tdo                                                     ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.723      ; 1.658      ;
; 51.349 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.787      ; 11.368     ;
; 51.349 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.787      ; 11.368     ;
; 51.349 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.787      ; 11.368     ;
; 51.349 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.787      ; 11.368     ;
; 51.539 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.786      ; 11.557     ;
; 51.539 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.786      ; 11.557     ;
; 51.539 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.786      ; 11.557     ;
; 51.539 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.786      ; 11.557     ;
; 51.539 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.786      ; 11.557     ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                 ;
+-------+--------------+----------------+-----------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                  ; Clock Edge ; Target                                                                                                                                                              ;
+-------+--------------+----------------+-----------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2                           ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT1                  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT10                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT11                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT12                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT13                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT14                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT15                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT16                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT17                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT18                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT19                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT2                  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT20                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT21                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT22                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT23                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT24                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT25                 ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT3                  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT4                  ;
; 3.576 ; 3.977        ; 0.401          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT5                  ;
+-------+--------------+----------------+-----------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                           ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+
; 9.891  ; 9.891        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                 ;
; 9.897  ; 9.897        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0]           ;
; 9.897  ; 9.897        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[1]           ;
; 9.897  ; 9.897        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|observablevcoout ;
; 9.916  ; 9.916        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|i                                 ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50~input|i                                 ;
; 10.083 ; 10.083       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|inclk[0]         ;
; 10.102 ; 10.102       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0]           ;
; 10.102 ; 10.102       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[1]           ;
; 10.102 ; 10.102       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|observablevcoout ;
; 10.109 ; 10.109       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                 ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                         ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+


+-----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK2_50'                                  ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock     ; Clock Edge ; Target    ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000       ; 4.000          ; Port Rate ; CLOCK2_50 ; Rise       ; CLOCK2_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+


+-----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK3_50'                                  ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock     ; Clock Edge ; Target    ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000       ; 4.000          ; Port Rate ; CLOCK3_50 ; Rise       ; CLOCK3_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                        ;
+--------+--------------+----------------+------------------+---------------------+------------+----------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                   ;
+--------+--------------+----------------+------------------+---------------------+------------+----------------------------------------------------------+
; 29.350 ; 49.954       ; 20.604         ; High Pulse Width ; altera_reserved_tck ; Fall       ; altera_internal_jtag~SHIFTUSER                           ;
; 29.442 ; 50.046       ; 20.604         ; Low Pulse Width  ; altera_reserved_tck ; Fall       ; altera_internal_jtag~SHIFTUSER                           ;
; 49.160 ; 49.380       ; 0.220          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|tdo                                     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|clr_reg                                 ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[0]                         ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[1]                         ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[2]                         ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][0]                           ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][1]                           ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][2]                           ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][3]                           ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[0]                             ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[1]                             ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[2]                             ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[3]                             ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[0]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[1]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[2]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[3]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[4]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[5]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[6]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[7]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[8]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[9]                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|reset_ena_reg                           ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][0]                    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][1]                    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][2]                    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][3]                    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0] ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1] ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2] ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3] ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4] ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[14]     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[15]     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[1]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[6]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]      ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[0]    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]    ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|tdo_bypass_reg                          ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|virtual_dr_scan_reg                     ;
; 49.220 ; 49.408       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|virtual_ir_scan_reg                     ;
; 49.221 ; 49.409       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[4]                             ;
; 49.221 ; 49.409       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|node_ena[1]~reg0                        ;
; 49.345 ; 49.345       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~TCKUTAPclkctrl|inclk[0]             ;
; 49.345 ; 49.345       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~TCKUTAPclkctrl|outclk               ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|clr_reg|clk                                     ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[0]|clk                     ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[1]|clk                     ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[2]|clk                     ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[3]|clk                     ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[0]|clk                ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[1]|clk                ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[2]|clk                ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[3]|clk                ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[4]|clk                ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_mode_reg[0]|clk                             ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_mode_reg[1]|clk                             ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_mode_reg[2]|clk                             ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][0]|clk                               ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][1]|clk                               ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][2]|clk                               ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][3]|clk                               ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[0]|clk                                 ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[1]|clk                                 ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[2]|clk                                 ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[3]|clk                                 ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[0]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[1]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[2]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[3]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[4]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[5]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[6]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[7]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[8]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[9]|clk                              ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|reset_ena_reg|clk                               ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_irf_reg[1][0]|clk                        ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_irf_reg[1][1]|clk                        ;
; 49.359 ; 49.359       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_irf_reg[1][2]|clk                        ;
+--------+--------------+----------------+------------------+---------------------+------------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Setup Times                                                                                  ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 0.152 ; 0.218 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 3.515 ; 3.865 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+----------------------------------------------------------------------------------------------+
; Hold Times                                                                                   ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 5.533 ; 5.312 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 3.996 ; 3.754 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                             ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 3.199  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 3.209  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 11.128 ; 10.808 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 8.039  ; 7.934  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 6.385  ; 6.370  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 9.224  ; 8.792  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 9.789  ; 9.602  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 7.497  ; 7.294  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 8.668  ; 8.528  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 8.754  ; 8.529  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 11.128 ; 10.808 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 7.055  ; 6.980  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 8.660  ; 8.396  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 9.114  ; 8.866  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 8.823  ; 8.466  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 7.210  ; 7.318  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 10.421 ; 10.126 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 7.531  ; 7.388  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 6.537  ; 6.527  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 8.219  ; 7.901  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 9.346  ; 9.187  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 7.119  ; 6.961  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 8.262  ; 8.173  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 8.072  ; 7.875  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 10.421 ; 10.126 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 7.038  ; 6.964  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 8.787  ; 8.593  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 9.136  ; 8.951  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 8.836  ; 8.532  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 6.303  ; 6.413  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 3.190  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 3.182  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;        ; 3.122  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;        ; 3.132  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;        ; 3.111  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;        ; 3.104  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 3.206  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 3.196  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;        ; 3.128  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;        ; 3.118  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 19.102 ; 19.794 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                     ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 2.592  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 2.602  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 5.641  ; 5.626  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 7.228  ; 7.127  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 5.641  ; 5.626  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 8.366  ; 7.950  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 8.909  ; 8.728  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 6.708  ; 6.512  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 7.832  ; 7.696  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 7.915  ; 7.698  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 10.193 ; 9.886  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 6.283  ; 6.210  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 7.824  ; 7.570  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 8.260  ; 8.020  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 7.980  ; 7.637  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 6.429  ; 6.534  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 5.559  ; 5.665  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 6.740  ; 6.601  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 5.785  ; 5.774  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 7.401  ; 7.095  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 8.483  ; 8.330  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 6.345  ; 6.192  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 7.442  ; 7.356  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 7.259  ; 7.069  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 9.513  ; 9.230  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 6.267  ; 6.194  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 7.945  ; 7.758  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 8.280  ; 8.102  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 7.992  ; 7.699  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 5.559  ; 5.665  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 2.583  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 2.575  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;        ; 2.516  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;        ; 2.526  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;        ; 2.506  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;        ; 2.499  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 2.599  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 2.589  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;        ; 2.522  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;        ; 2.512  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 16.506 ; 17.199 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                             ;
+------------+-----------------+----------------------------------------+-------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                             ; Note                                                  ;
+------------+-----------------+----------------------------------------+-------------------------------------------------------+
; 84.52 MHz  ; 24.72 MHz       ; altera_reserved_tck                    ; limit due to high minimum pulse width violation (tch) ;
; 202.22 MHz ; 200.0 MHz       ; U1|pll_100|altpll_component|pll|clk[0] ; limit due to minimum period restriction (tmin)        ;
+------------+-----------------+----------------------------------------+-------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                              ;
+----------------------------------------+--------+---------------+
; Clock                                  ; Slack  ; End Point TNS ;
+----------------------------------------+--------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 3.055  ; 0.000         ;
; altera_reserved_tck                    ; 44.084 ; 0.000         ;
+----------------------------------------+--------+---------------+


+----------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                              ;
+----------------------------------------+-------+---------------+
; Clock                                  ; Slack ; End Point TNS ;
+----------------------------------------+-------+---------------+
; altera_reserved_tck                    ; 0.228 ; 0.000         ;
; U1|pll_100|altpll_component|pll|clk[0] ; 0.379 ; 0.000         ;
+----------------------------------------+-------+---------------+


+----------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary        ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 43.850 ; 0.000         ;
+---------------------+--------+---------------+


+----------------------------------------------+
; Slow 1200mV 0C Model Removal Summary         ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; -2.375 ; -2.375        ;
+---------------------+--------+---------------+


+-----------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                ;
+----------------------------------------+--------+---------------+
; Clock                                  ; Slack  ; End Point TNS ;
+----------------------------------------+--------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 3.000  ; 0.000         ;
; CLOCK_50                               ; 9.882  ; 0.000         ;
; CLOCK2_50                              ; 16.000 ; 0.000         ;
; CLOCK3_50                              ; 16.000 ; 0.000         ;
; altera_reserved_tck                    ; 29.775 ; 0.000         ;
+----------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                                                                  ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                             ; To Node                                                                                                                    ; Launch Clock                           ; Latch Clock                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; 3.055 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 4.883      ;
; 3.081 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 4.857      ;
; 3.095 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 4.843      ;
; 3.109 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 4.829      ;
; 3.130 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.758      ;
; 3.130 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.758      ;
; 3.130 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.758      ;
; 3.130 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.758      ;
; 3.134 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.753      ;
; 3.134 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.753      ;
; 3.134 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.753      ;
; 3.134 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.753      ;
; 3.134 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.753      ;
; 3.140 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.748      ;
; 3.140 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.748      ;
; 3.140 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.748      ;
; 3.159 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.092     ; 4.751      ;
; 3.165 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.118     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][2]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.168 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][1]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.115     ; 4.719      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[15]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[14]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[13]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[12]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[11]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[10]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[0]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[7]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[6]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[5]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[4]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[3]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[2]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[1]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.171 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[16]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.121     ; 4.710      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][2]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.195 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][1]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.114     ; 4.693      ;
; 3.215 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.078     ; 4.709      ;
; 3.215 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][6]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.104     ; 4.683      ;
; 3.218 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 4.720      ;
; 3.219 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.072     ; 4.711      ;
; 3.221 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][2]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.104     ; 4.677      ;
; 3.222 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.084     ; 4.696      ;
; 3.232 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.074     ; 4.696      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.237 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.113     ; 4.652      ;
; 3.238 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][6]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.091     ; 4.673      ;
; 3.238 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][7]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 4.700      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_13_pp|data_out[6]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[7]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[6]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_13_pp|data_out[5]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_13_pp|data_out[4]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[5]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[4]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[3]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[2]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[1]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[0]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[11]        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[12]        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[15]        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.293 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp|data_out[16]        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.124     ; 4.585      ;
; 3.295 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_5_n|pipe[0][10]            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][19] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.076     ; 4.631      ;
; 3.295 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][23]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.084     ; 4.623      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][21] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][20] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][19] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][18] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][17] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][15] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_6_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][22] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.299 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_2 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n|pipe[0][23] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.106     ; 4.597      ;
; 3.302 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][0]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.104     ; 4.596      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                  ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                ; To Node                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 44.084 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.539      ; 8.457      ;
; 44.084 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.539      ; 8.457      ;
; 44.084 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.539      ; 8.457      ;
; 44.084 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.539      ; 8.457      ;
; 44.084 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.539      ; 8.457      ;
; 44.274 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.015     ; 5.713      ;
; 44.336 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.207      ;
; 44.340 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.203      ;
; 44.344 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.199      ;
; 44.346 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.197      ;
; 44.391 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.152      ;
; 44.408 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.135      ;
; 44.490 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.053      ;
; 44.495 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.048      ;
; 44.512 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.031      ;
; 44.535 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 8.008      ;
; 44.575 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 7.968      ;
; 44.610 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 7.933      ;
; 44.799 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.540      ; 7.743      ;
; 44.799 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.540      ; 7.743      ;
; 44.799 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.540      ; 7.743      ;
; 44.799 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.540      ; 7.743      ;
; 45.303 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 2.541      ; 7.240      ;
; 45.674 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.159     ; 4.169      ;
; 45.839 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.015     ; 4.148      ;
; 46.206 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0] ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.160     ; 3.636      ;
; 46.506 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.923      ; 4.419      ;
; 46.910 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; -0.160     ; 2.932      ;
; 47.173 ; sld_hub:auto_hub|irsr_reg[0]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.913      ; 3.742      ;
; 47.256 ; sld_hub:auto_hub|irsr_reg[1]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.913      ; 3.659      ;
; 47.485 ; sld_hub:auto_hub|irsr_reg[2]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.913      ; 3.430      ;
; 47.710 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.914      ; 3.206      ;
; 48.438 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.915      ; 2.479      ;
; 48.442 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.915      ; 2.475      ;
; 48.832 ; sld_hub:auto_hub|tdo_bypass_reg                                          ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.915      ; 2.085      ;
; 49.296 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.922      ; 1.628      ;
; 94.501 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 5.420      ;
; 94.731 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 3.216      ;
; 94.731 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 3.216      ;
; 94.731 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 3.216      ;
; 94.731 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 3.216      ;
; 94.731 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 3.216      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 94.964 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -2.055     ; 2.983      ;
; 95.048 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 4.872      ;
; 95.186 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 4.742      ;
; 95.334 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.073     ; 4.595      ;
; 95.359 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.564      ;
; 95.359 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.564      ;
; 95.359 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.564      ;
; 95.359 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.564      ;
; 95.379 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[15]                     ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.094     ; 4.529      ;
; 95.495 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.426      ;
; 95.495 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.426      ;
; 95.495 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[2]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 4.426      ;
; 95.515 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.416      ;
; 95.515 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.416      ;
; 95.515 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[2]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.416      ;
; 95.587 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 4.343      ;
; 95.671 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.252      ;
; 95.671 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.252      ;
; 95.671 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.252      ;
; 95.671 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.252      ;
; 95.703 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 4.227      ;
; 95.780 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 4.142      ;
; 95.803 ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.089     ; 4.110      ;
; 95.836 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|hub_mode_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 4.086      ;
; 95.849 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.074      ;
; 95.849 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.074      ;
; 95.849 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.074      ;
; 95.849 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.074      ;
; 95.855 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.512     ; 2.635      ;
; 95.919 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 3.993      ;
; 95.919 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 3.993      ;
; 95.919 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 3.993      ;
; 95.919 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 3.993      ;
; 95.919 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 3.993      ;
; 95.924 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 4.006      ;
; 95.933 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.998      ;
; 95.933 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.998      ;
; 95.933 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.998      ;
; 95.933 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.998      ;
; 95.940 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.512     ; 2.550      ;
; 95.952 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 3.978      ;
; 96.001 ; sld_hub:auto_hub|irsr_reg[0]                                             ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.083     ; 3.918      ;
; 96.006 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 3.906      ;
; 96.051 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.512     ; 2.439      ;
; 96.058 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.088     ; 3.856      ;
; 96.061 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.365     ; 2.576      ;
; 96.061 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.365     ; 2.576      ;
; 96.061 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.365     ; 2.576      ;
; 96.061 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.365     ; 2.576      ;
; 96.061 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.365     ; 2.576      ;
; 96.078 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 3.842      ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                   ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                 ; To Node                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.228 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.762      ;
; 0.265 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.010      ; 1.470      ;
; 0.395 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.929      ;
; 0.395 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.929      ;
; 0.395 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.929      ;
; 0.395 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.929      ;
; 0.395 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 2.339      ; 2.929      ;
; 0.397 ; sld_hub:auto_hub|tdo                                                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.077      ; 0.669      ;
; 0.462 ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.738      ;
; 0.468 ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.744      ;
; 0.471 ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.747      ;
; 0.471 ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.747      ;
; 0.498 ; sld_hub:auto_hub|irf_reg[1][0]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.010      ; 1.703      ;
; 0.605 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.009      ; 1.809      ;
; 0.637 ; sld_hub:auto_hub|jtag_ir_reg[9]                                           ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.913      ;
; 0.639 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.915      ;
; 0.639 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.915      ;
; 0.640 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.916      ;
; 0.646 ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.922      ;
; 0.646 ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 0.922      ;
; 0.654 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 0.931      ;
; 0.767 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.009      ; 1.971      ;
; 0.781 ; sld_hub:auto_hub|irf_reg[1][1]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.009      ; 1.985      ;
; 0.811 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.087      ;
; 0.812 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.088      ;
; 0.814 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.090      ;
; 0.844 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.120      ;
; 0.856 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.132      ;
; 0.859 ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.135      ;
; 0.874 ; sld_hub:auto_hub|irf_reg[1][0]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.009      ; 2.078      ;
; 0.908 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.163      ; 2.266      ;
; 0.908 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.163      ; 2.266      ;
; 0.908 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.163      ; 2.266      ;
; 0.908 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.163      ; 2.266      ;
; 0.956 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.232      ;
; 0.967 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.243      ;
; 0.970 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.246      ;
; 0.976 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[14]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.252      ;
; 1.014 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.291      ;
; 1.017 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.294      ;
; 1.017 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.293      ;
; 1.017 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.293      ;
; 1.017 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.293      ;
; 1.018 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|irf_reg[1][2]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.294      ;
; 1.019 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.295      ;
; 1.021 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.298      ;
; 1.040 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.316      ;
; 1.047 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.323      ;
; 1.047 ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.323      ;
; 1.049 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.162      ; 2.406      ;
; 1.049 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.162      ; 2.406      ;
; 1.049 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.162      ; 2.406      ;
; 1.049 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.162      ; 2.406      ;
; 1.049 ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.162      ; 2.406      ;
; 1.053 ; sld_hub:auto_hub|irf_reg[1][0]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.009      ; 2.257      ;
; 1.056 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.332      ;
; 1.063 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.339      ;
; 1.070 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.345      ;
; 1.105 ; sld_hub:auto_hub|irf_reg[1][0]                                            ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.009      ; 2.309      ;
; 1.110 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.386      ;
; 1.147 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.423      ;
; 1.148 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.424      ;
; 1.153 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.429      ;
; 1.157 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.433      ;
; 1.159 ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.083      ; 1.437      ;
; 1.165 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.441      ;
; 1.173 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.448      ;
; 1.173 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.448      ;
; 1.173 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.448      ;
; 1.173 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.448      ;
; 1.173 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.448      ;
; 1.191 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.468      ;
; 1.197 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.474      ;
; 1.201 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.477      ;
; 1.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.487      ;
; 1.216 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|virtual_ir_scan_reg                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.491      ;
; 1.228 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                       ; sld_hub:auto_hub|reset_ena_reg                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.075      ; 1.498      ;
; 1.228 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.505      ;
; 1.233 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.510      ;
; 1.234 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|virtual_dr_scan_reg                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.509      ;
; 1.259 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.536      ;
; 1.264 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|irf_reg[1][1]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.540      ;
; 1.267 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.543      ;
; 1.272 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.549      ;
; 1.274 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.551      ;
; 1.280 ; sld_hub:auto_hub|tdo_bypass_reg                                           ; sld_hub:auto_hub|tdo_bypass_reg                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.556      ;
; 1.280 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.556      ;
; 1.281 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.557      ;
; 1.290 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.566      ;
; 1.335 ; sld_hub:auto_hub|irf_reg[1][2]                                            ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.611      ;
; 1.336 ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; sld_hub:auto_hub|irf_reg[1][0]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.612      ;
; 1.364 ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; sld_hub:auto_hub|irf_reg[1][2]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.640      ;
; 1.364 ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; sld_hub:auto_hub|irf_reg[1][1]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.640      ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                              ; To Node                                                                                                                                                                                                                                                ; Launch Clock                           ; Latch Clock                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; 0.379 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[6]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.043      ;
; 0.385 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[8]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.049      ;
; 0.386 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[6]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.042      ;
; 0.388 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[2]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.052      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|empty_dff                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|empty_dff                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|usedw_is_0_dff                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|usedw_is_0_dff                                         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[0]                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[0]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[1]                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[1]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[2]                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[2]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[2]                                                                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[2]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[3]                                                                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[3]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.391 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.669      ;
; 0.392 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|was_stalled                                                                                                                ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|was_stalled                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.669      ;
; 0.394 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[10]                                                                                                           ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.058      ;
; 0.398 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[7]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.062      ;
; 0.400 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[3]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.092      ;
; 0.400 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[3]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.092      ;
; 0.404 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[1]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.068      ;
; 0.405 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[0]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.069      ;
; 0.406 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[4]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.070      ;
; 0.406 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[6]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.062      ;
; 0.407 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|rd_ptr_lsb                             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|rd_ptr_lsb                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.684      ;
; 0.408 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated|pipeline_dffe[0]                                                                                                 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated|pipeline_dffe[0]                                                                                                                 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.081      ; 0.684      ;
; 0.409 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[3]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.065      ;
; 0.409 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[5]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.065      ;
; 0.410 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[11]                                                                                                           ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.074      ;
; 0.412 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cs[7]                                                                                                                                                   ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.068      ;
; 0.412 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[4]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.104      ;
; 0.412 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[4]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.104      ;
; 0.414 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[9]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.078      ;
; 0.415 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[12]                                                                                                           ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.079      ;
; 0.415 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[7]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.071      ;
; 0.415 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[1]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.107      ;
; 0.415 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[1]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.107      ;
; 0.416 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[5]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.080      ;
; 0.419 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[2]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.075      ;
; 0.423 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[0]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.079      ;
; 0.435 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[3]                                                                                                            ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.434      ; 1.099      ;
; 0.436 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[5]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.128      ;
; 0.436 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[5]                                                                                                                                              ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.462      ; 1.128      ;
; 0.444 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_ready_s                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.722      ;
; 0.445 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002|dxxpdo[20]                                                                                                                                                         ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[7]                                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.722      ;
; 0.448 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.726      ;
; 0.449 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002|dxxpdo[19]                                                                                                                                                         ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[6]                                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.726      ;
; 0.449 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[4]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.105      ;
; 0.453 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[14]                                                                                                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[0]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.730      ;
; 0.456 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[1]                                                                                                                                                    ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.426      ; 1.112      ;
; 0.458 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc0n|data_out[12]                                                                                                                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_0_sym_add|res[13]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.735      ;
; 0.458 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][23]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][23]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.736      ;
; 0.458 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|sink_stall_reg                                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|valid_ctrl_int                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.736      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][20]                                                                                                             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][20]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][12]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][12]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[9]                                                                                                                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[9]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][7]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][7]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_unb:wr_ptr|counter_reg_bit[2]     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_unb:wr_ptr|counter_reg_bit[2]                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_2_n|pipe[0][8]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_1_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_tnb:rd_ptr_msb|counter_reg_bit[1] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_tnb:rd_ptr_msb|counter_reg_bit[1]                 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][2]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][2]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.459 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][2]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][2]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n|pipe[0][8]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_8_pp|data_out[0]                                                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_10_pp|data_out[0]                                                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_5_n|pipe[0][10]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[12]                                                                                            ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[12]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[7]                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[7]                                                                                                                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[6]                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[6]                                                                                                                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[3]                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[3]                                                                                                                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[1]                                                                                                                                                      ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[2]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[0]                                                                                                                                                      ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[1]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][11]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][11]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][10]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][10]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[7]                                                                                                                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[7]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[4]                                                                                                                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[4]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][3]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][3]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][1]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][1]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][0]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_8_pp|data_out[0]                                                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][1]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][1]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][2]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][2]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][1]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][1]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_0_n|pipe[0][0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][32]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][32]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][21]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|data_int[0]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_6_n|pipe[0][13]                                                                                                             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_3_n|pipe[0][13]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_6_n|pipe[0][12]                                                                                                             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_3_n|pipe[0][12]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_6_pp|data_out[0]                                                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.737      ;
; 0.460 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_4_pp|data_out[0]                                                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_2_n|pipe[0][4]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.083      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][18]                                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][18]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[12]                                                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[12]                                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_6_n|pipe[0][12]                                                                                                             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_3_n|pipe[0][12]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][9]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_1_n|pipe[0][9]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_6_pp|data_out[0]                                                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[24]                                                                                            ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[24]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
; 0.461 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[14]                                                                                            ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[14]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.082      ; 0.738      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                            ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                                  ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 43.850 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.009      ; 13.161     ;
; 43.850 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.009      ; 13.161     ;
; 43.850 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.009      ; 13.161     ;
; 43.850 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.009      ; 13.161     ;
; 43.850 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.009      ; 13.161     ;
; 44.031 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.010      ; 12.981     ;
; 44.031 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.010      ; 12.981     ;
; 44.031 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.010      ; 12.981     ;
; 44.031 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.010      ; 12.981     ;
; 47.328 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 7.011      ; 9.685      ;
; 49.317 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]    ; sld_hub:auto_hub|tdo                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.915      ; 1.600      ;
; 90.272 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.374     ; 8.356      ;
; 90.272 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.374     ; 8.356      ;
; 90.272 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.374     ; 8.356      ;
; 90.272 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.374     ; 8.356      ;
; 90.272 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.374     ; 8.356      ;
; 90.499 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.373     ; 8.130      ;
; 90.499 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.373     ; 8.130      ;
; 90.499 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.373     ; 8.130      ;
; 90.499 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.373     ; 8.130      ;
; 93.178 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.009      ; 13.833     ;
; 93.178 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.009      ; 13.833     ;
; 93.178 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.009      ; 13.833     ;
; 93.178 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.009      ; 13.833     ;
; 93.178 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.009      ; 13.833     ;
; 93.405 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.010      ; 13.607     ;
; 93.405 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.010      ; 13.607     ;
; 93.405 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.010      ; 13.607     ;
; 93.405 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.010      ; 13.607     ;
; 97.643 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 2.279      ;
; 97.791 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 7.011      ; 9.222      ;
; 97.927 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[3]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.994      ;
; 97.938 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; sld_hub:auto_hub|hub_mode_reg[2]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 1.974      ;
; 97.983 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[4]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.091     ; 1.928      ;
; 97.983 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.091     ; 1.928      ;
; 97.995 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 1.927      ;
; 98.042 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.083     ; 1.877      ;
; 98.207 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 1.715      ;
; 98.207 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 1.715      ;
; 98.207 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.080     ; 1.715      ;
; 98.278 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 1.642      ;
; 98.278 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_dr_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 1.642      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.314 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.607      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[8]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[7]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[9]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[6]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[2]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[5]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[4]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.440 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[3]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.481      ;
; 98.504 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[0]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.417      ;
; 98.504 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[1]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.417      ;
; 98.504 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[2]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.417      ;
; 98.504 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[0]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 1.417      ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                             ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                                  ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; -2.375 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.211      ; 7.031      ;
; 1.020  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[0]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.296      ;
; 1.020  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[1]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.296      ;
; 1.020  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[2]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.296      ;
; 1.020  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[0]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.296      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[8]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[7]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[9]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[6]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[2]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[5]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[4]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.093  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[3]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.369      ;
; 1.206  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.481      ;
; 1.206  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_dr_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.481      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.259  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.535      ;
; 1.349  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.624      ;
; 1.349  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.624      ;
; 1.349  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.624      ;
; 1.414  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.082      ; 1.691      ;
; 1.472  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.079      ; 1.746      ;
; 1.484  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; sld_hub:auto_hub|hub_mode_reg[2]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.750      ;
; 1.510  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[4]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.776      ;
; 1.510  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.776      ;
; 1.579  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[3]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 1.855      ;
; 1.769  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.210      ; 11.174     ;
; 1.769  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.210      ; 11.174     ;
; 1.769  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.210      ; 11.174     ;
; 1.769  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.210      ; 11.174     ;
; 1.784  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.081      ; 2.060      ;
; 1.987  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.209      ; 11.391     ;
; 1.987  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.209      ; 11.391     ;
; 1.987  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.209      ; 11.391     ;
; 1.987  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.209      ; 11.391     ;
; 1.987  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 9.209      ; 11.391     ;
; 5.620  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.154      ; 6.969      ;
; 5.620  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.154      ; 6.969      ;
; 5.620  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.154      ; 6.969      ;
; 5.620  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.154      ; 6.969      ;
; 5.794  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.153      ; 7.142      ;
; 5.794  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.153      ; 7.142      ;
; 5.794  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.153      ; 7.142      ;
; 5.794  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.153      ; 7.142      ;
; 5.794  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.153      ; 7.142      ;
; 48.050 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.211      ; 7.476      ;
; 50.200 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]    ; sld_hub:auto_hub|tdo                                                     ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 1.116      ; 1.531      ;
; 51.140 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.210      ; 10.565     ;
; 51.140 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.210      ; 10.565     ;
; 51.140 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.210      ; 10.565     ;
; 51.140 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.210      ; 10.565     ;
; 51.314 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.209      ; 10.738     ;
; 51.314 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.209      ; 10.738     ;
; 51.314 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.209      ; 10.738     ;
; 51.314 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.209      ; 10.738     ;
; 51.314 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 9.209      ; 10.738     ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                  ;
+-------+--------------+----------------+-----------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                  ; Clock Edge ; Target                                                                                                                                                              ;
+-------+--------------+----------------+-----------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12 ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8  ;
; 3.000 ; 8.000        ; 5.000          ; Min Period      ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2                           ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT1                  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT10                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT11                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT12                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT13                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT14                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT15                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT16                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT17                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT18                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT19                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT2                  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT20                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT21                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT22                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT23                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT24                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT25                 ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT3                  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT4                  ;
; 3.590 ; 3.972        ; 0.382          ; Low Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|mac_out2~DATAOUT5                  ;
+-------+--------------+----------------+-----------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                 ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                           ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+
; 9.882  ; 9.882        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0]           ;
; 9.882  ; 9.882        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[1]           ;
; 9.882  ; 9.882        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|observablevcoout ;
; 9.904  ; 9.904        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                 ;
; 9.920  ; 9.920        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|i                                 ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50~input|i                                 ;
; 10.079 ; 10.079       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|inclk[0]         ;
; 10.096 ; 10.096       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                 ;
; 10.115 ; 10.115       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0]           ;
; 10.115 ; 10.115       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[1]           ;
; 10.115 ; 10.115       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                         ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+


+-----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50'                                   ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock     ; Clock Edge ; Target    ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000       ; 4.000          ; Port Rate ; CLOCK2_50 ; Rise       ; CLOCK2_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+


+-----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50'                                   ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock     ; Clock Edge ; Target    ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000       ; 4.000          ; Port Rate ; CLOCK3_50 ; Rise       ; CLOCK3_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                         ;
+--------+--------------+----------------+------------------+---------------------+------------+----------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                   ;
+--------+--------------+----------------+------------------+---------------------+------------+----------------------------------------------------------+
; 29.775 ; 49.975       ; 20.200         ; High Pulse Width ; altera_reserved_tck ; Fall       ; altera_internal_jtag~SHIFTUSER                           ;
; 29.825 ; 50.025       ; 20.200         ; Low Pulse Width  ; altera_reserved_tck ; Fall       ; altera_internal_jtag~SHIFTUSER                           ;
; 48.768 ; 48.984       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|tdo                                     ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[1]                         ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[2]                         ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[4]                             ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|node_ena[1]~reg0                        ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|reset_ena_reg                           ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0] ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1] ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2] ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3] ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4] ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]      ;
; 48.813 ; 48.997       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|tdo_bypass_reg                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|clr_reg                                 ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[0]                         ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][0]                           ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][1]                           ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][2]                           ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][3]                           ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[0]                             ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[1]                             ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[2]                             ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[3]                             ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[0]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[1]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[2]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[3]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[4]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[5]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[6]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[7]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[8]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[9]                          ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][0]                    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][1]                    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][2]                    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][3]                    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[14]     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[15]     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[1]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[6]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]      ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[0]    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]    ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|virtual_dr_scan_reg                     ;
; 48.814 ; 48.998       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|virtual_ir_scan_reg                     ;
; 48.928 ; 48.928       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~TCKUTAPclkctrl|inclk[0]             ;
; 48.928 ; 48.928       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~TCKUTAPclkctrl|outclk               ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[0]|clk                     ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[1]|clk                     ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[3]|clk                     ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[0]|clk                ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[1]|clk                ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[2]|clk                ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[3]|clk                ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|word_counter[4]|clk                ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_mode_reg[1]|clk                             ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_mode_reg[2]|clk                             ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[4]|clk                                 ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|node_ena[1]~reg0|clk                            ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|reset_ena_reg|clk                               ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_jsm|state[3]|clk                         ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_jsm|state[4]|clk                         ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_jsm|state[5]|clk                         ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|shadow_jsm|state[7]|clk                         ;
; 48.943 ; 48.943       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|tdo_bypass_reg|clk                              ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|clr_reg|clk                                     ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_info_reg|WORD_SR[2]|clk                     ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|hub_mode_reg[0]|clk                             ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][0]|clk                               ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][1]|clk                               ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][2]|clk                               ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irf_reg[1][3]|clk                               ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[0]|clk                                 ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[1]|clk                                 ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[2]|clk                                 ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|irsr_reg[3]|clk                                 ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[0]|clk                              ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[1]|clk                              ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[2]|clk                              ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[3]|clk                              ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[4]|clk                              ;
; 48.944 ; 48.944       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; auto_hub|jtag_ir_reg[5]|clk                              ;
+--------+--------------+----------------+------------------+---------------------+------------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Setup Times                                                                                  ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 0.588 ; 0.558 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 3.733 ; 4.244 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+----------------------------------------------------------------------------------------------+
; Hold Times                                                                                   ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 4.868 ; 4.517 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 3.284 ; 2.989 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                             ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 2.976  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 2.986  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 10.579 ; 9.772  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 7.625  ; 7.190  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 6.015  ; 5.809  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 8.781  ; 7.947  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 9.285  ; 8.697  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 7.103  ; 6.620  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 8.209  ; 7.735  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 8.296  ; 7.749  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 10.579 ; 9.772  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 6.656  ; 6.346  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 8.194  ; 7.618  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 8.655  ; 8.017  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 8.367  ; 7.669  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 6.535  ; 6.908  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 9.882  ; 9.167  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 7.128  ; 6.714  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 6.172  ; 5.942  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 7.812  ; 7.145  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 8.858  ; 8.326  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 6.740  ; 6.320  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 7.817  ; 7.418  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 7.631  ; 7.160  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 9.882  ; 9.167  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 6.640  ; 6.331  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 8.308  ; 7.786  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 8.671  ; 8.093  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 8.373  ; 7.725  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 5.722  ; 6.047  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 2.965  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 2.958  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;        ; 2.867  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;        ; 2.877  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;        ; 2.858  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;        ; 2.850  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 2.984  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 2.974  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;        ; 2.873  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;        ; 2.863  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 17.951 ; 18.474 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                     ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 2.422  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 2.432  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 5.333  ; 5.134  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 6.878  ; 6.459  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 5.333  ; 5.134  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 7.988  ; 7.185  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 8.472  ; 7.906  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 6.376  ; 5.911  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 7.438  ; 6.982  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 7.522  ; 6.996  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 9.713  ; 8.937  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 5.947  ; 5.648  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 7.423  ; 6.869  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 7.866  ; 7.252  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 7.589  ; 6.918  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 5.827  ; 6.188  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 5.047  ; 5.260  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 6.399  ; 6.000  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 5.482  ; 5.260  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 7.057  ; 6.415  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 8.061  ; 7.549  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 6.028  ; 5.624  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 7.062  ; 6.677  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 6.882  ; 6.428  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 9.043  ; 8.355  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 5.931  ; 5.633  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 7.533  ; 7.030  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 7.881  ; 7.324  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 7.594  ; 6.971  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 5.047  ; 5.360  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 2.412  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 2.406  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;        ; 2.316  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;        ; 2.326  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;        ; 2.308  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;        ; 2.300  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 2.431  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 2.421  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;        ; 2.322  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;        ; 2.312  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 15.414 ; 15.939 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                              ;
+----------------------------------------+--------+---------------+
; Clock                                  ; Slack  ; End Point TNS ;
+----------------------------------------+--------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 5.539  ; 0.000         ;
; altera_reserved_tck                    ; 47.627 ; 0.000         ;
+----------------------------------------+--------+---------------+


+----------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                              ;
+----------------------------------------+-------+---------------+
; Clock                                  ; Slack ; End Point TNS ;
+----------------------------------------+-------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 0.130 ; 0.000         ;
; altera_reserved_tck                    ; 0.181 ; 0.000         ;
+----------------------------------------+-------+---------------+


+----------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary        ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 46.617 ; 0.000         ;
+---------------------+--------+---------------+


+----------------------------------------------+
; Fast 1200mV 0C Model Removal Summary         ;
+---------------------+--------+---------------+
; Clock               ; Slack  ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; -0.992 ; -0.992        ;
+---------------------+--------+---------------+


+-----------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                ;
+----------------------------------------+--------+---------------+
; Clock                                  ; Slack  ; End Point TNS ;
+----------------------------------------+--------+---------------+
; U1|pll_100|altpll_component|pll|clk[0] ; 3.753  ; 0.000         ;
; CLOCK_50                               ; 9.400  ; 0.000         ;
; CLOCK2_50                              ; 16.000 ; 0.000         ;
; CLOCK3_50                              ; 16.000 ; 0.000         ;
; altera_reserved_tck                    ; 29.420 ; 0.000         ;
+----------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                                                                  ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                             ; To Node                                                                                                                    ; Launch Clock                           ; Latch Clock                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; 5.539 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 2.384      ;
; 5.539 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 2.384      ;
; 5.539 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 2.384      ;
; 5.539 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 2.384      ;
; 5.539 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.064     ; 2.384      ;
; 5.547 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.377      ;
; 5.547 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.377      ;
; 5.547 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.377      ;
; 5.547 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.377      ;
; 5.549 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][14] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.376      ;
; 5.549 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.376      ;
; 5.549 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][12] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.376      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][2]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.559 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][1]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.365      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][2]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.575 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][1]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.350      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][11] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][10] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][9]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][8]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][7]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][6]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][5]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][4]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.604 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg          ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][3]  ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.062     ; 2.321      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[15]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[14]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[13]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[12]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[11]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[10]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[0]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[7]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[6]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[5]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[4]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[3]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[2]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[1]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.605 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp|data_out[16]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.313      ;
; 5.612 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.030     ; 2.345      ;
; 5.619 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.030     ; 2.338      ;
; 5.635 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.039     ; 2.313      ;
; 5.648 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.030     ; 2.309      ;
; 5.655 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.065     ; 2.267      ;
; 5.656 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n|pipe[0][4]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.030     ; 2.301      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[16]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[0]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[3]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[2]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[1]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[2]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.669 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[1]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.066     ; 2.252      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[16]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[15]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[14]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[13]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[12]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[11]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[10]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[7]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[6]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[5]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[4]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.680 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp|data_out[3]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.069     ; 2.238      ;
; 5.686 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][3]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][15]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.056     ; 2.245      ;
; 5.695 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n|pipe[0][7]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.030     ; 2.262      ;
; 5.698 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][23]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.039     ; 2.250      ;
; 5.700 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][33]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.052     ; 2.235      ;
; 5.704 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][32]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.052     ; 2.231      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[15]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[14]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[13]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[12]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[11]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[10]         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[0]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[7]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[6]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[5]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.709 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|stall_reg~SynDup_1 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp|data_out[4]          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.068     ; 2.210      ;
; 5.712 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][33]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.045     ; 2.230      ;
; 5.714 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.040     ; 2.233      ;
; 5.714 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][13] ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.037     ; 2.236      ;
; 5.716 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][9]               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][32]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.045     ; 2.226      ;
; 5.717 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n|pipe[0][5]             ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n|pipe[0][18]   ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 8.000        ; -0.063     ; 2.207      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                  ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                ; To Node                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 47.627 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.322      ; 2.682      ;
; 47.706 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.249      ; 3.530      ;
; 47.706 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.249      ; 3.530      ;
; 47.706 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.249      ; 3.530      ;
; 47.706 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.249      ; 3.530      ;
; 47.706 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.249      ; 3.530      ;
; 47.789 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.450      ;
; 47.796 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.443      ;
; 47.797 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.442      ;
; 47.799 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.440      ;
; 47.809 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.251      ; 3.429      ;
; 47.816 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.251      ; 3.422      ;
; 47.850 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.389      ;
; 47.856 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.383      ;
; 47.862 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.377      ;
; 47.883 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.251      ; 3.355      ;
; 47.896 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.252      ; 3.343      ;
; 47.907 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.251      ; 3.331      ;
; 48.009 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.250      ; 3.228      ;
; 48.009 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.250      ; 3.228      ;
; 48.009 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.250      ; 3.228      ;
; 48.009 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.250      ; 3.228      ;
; 48.049 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.028      ; 1.966      ;
; 48.229 ; altera_internal_jtag~SHIFTUSER                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 1.251      ; 3.009      ;
; 48.331 ; sld_hub:auto_hub|irsr_reg[0]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.018      ; 1.674      ;
; 48.359 ; sld_hub:auto_hub|irsr_reg[1]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.018      ; 1.646      ;
; 48.360 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.265      ; 1.892      ;
; 48.387 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.322      ; 1.922      ;
; 48.482 ; sld_hub:auto_hub|irsr_reg[2]                                             ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.018      ; 1.523      ;
; 48.511 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.019      ; 1.495      ;
; 48.582 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0] ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.263      ; 1.668      ;
; 48.842 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.020      ; 1.165      ;
; 48.907 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.020      ; 1.100      ;
; 48.920 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.263      ; 1.330      ;
; 49.079 ; sld_hub:auto_hub|tdo_bypass_reg                                          ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.020      ; 0.928      ;
; 49.273 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.026      ; 0.740      ;
; 97.418 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.377     ; 1.192      ;
; 97.437 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.377     ; 1.173      ;
; 97.473 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.377     ; 1.137      ;
; 97.488 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 2.458      ;
; 97.501 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.314     ; 1.172      ;
; 97.501 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.314     ; 1.172      ;
; 97.501 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.314     ; 1.172      ;
; 97.501 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.314     ; 1.172      ;
; 97.501 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.314     ; 1.172      ;
; 97.557 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.313     ; 1.117      ;
; 97.557 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.313     ; 1.117      ;
; 97.557 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.313     ; 1.117      ;
; 97.557 ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.313     ; 1.117      ;
; 97.588 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.887     ; 1.512      ;
; 97.588 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.887     ; 1.512      ;
; 97.588 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.887     ; 1.512      ;
; 97.588 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.887     ; 1.512      ;
; 97.588 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.887     ; 1.512      ;
; 97.604 ; sld_hub:auto_hub|irf_reg[1][1]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.377     ; 1.006      ;
; 97.617 ; sld_hub:auto_hub|irf_reg[1][1]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.377     ; 0.993      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.681 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.886     ; 1.420      ;
; 97.688 ; sld_hub:auto_hub|irf_reg[1][1]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.377     ; 0.922      ;
; 97.699 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.043     ; 2.245      ;
; 97.735 ; sld_hub:auto_hub|irf_reg[1][0]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.376     ; 0.876      ;
; 97.836 ; sld_hub:auto_hub|irf_reg[1][1]                                           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.376     ; 0.775      ;
; 97.878 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[15]                     ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 2.054      ;
; 97.885 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 2.062      ;
; 97.885 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 2.062      ;
; 97.885 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 2.062      ;
; 97.885 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[7]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 2.062      ;
; 97.899 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 2.053      ;
; 97.907 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.047      ;
; 97.980 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.967      ;
; 97.980 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.967      ;
; 97.980 ; sld_hub:auto_hub|irsr_reg[3]                                             ; sld_hub:auto_hub|irsr_reg[2]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.967      ;
; 98.009 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 1.947      ;
; 98.009 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 1.947      ;
; 98.009 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|irsr_reg[2]                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 1.947      ;
; 98.041 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.906      ;
; 98.041 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.906      ;
; 98.041 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.906      ;
; 98.041 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.906      ;
; 98.054 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.900      ;
; 98.062 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|hub_mode_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.885      ;
; 98.078 ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; sld_hub:auto_hub|node_ena[1]~reg0                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.049     ; 1.860      ;
; 98.110 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.837      ;
; 98.110 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.837      ;
; 98.110 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.837      ;
; 98.110 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                      ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 1.837      ;
; 98.130 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                      ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.816      ;
; 98.142 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 1.813      ;
; 98.142 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 1.813      ;
; 98.142 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 1.813      ;
; 98.142 ; sld_hub:auto_hub|irsr_reg[4]                                             ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 1.813      ;
; 98.158 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[2]                       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 1.796      ;
; 98.167 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 1.770      ;
; 98.167 ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 1.770      ;
+--------+--------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                                ; Launch Clock                           ; Latch Clock                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+
; 0.130 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[3]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.249      ; 0.483      ;
; 0.131 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[3]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.247      ; 0.482      ;
; 0.136 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[6]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.466      ;
; 0.137 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[2]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.467      ;
; 0.137 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[6]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.463      ;
; 0.137 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[4]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.249      ; 0.490      ;
; 0.138 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[8]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.468      ;
; 0.138 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[10]                                                                                    ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.468      ;
; 0.138 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[4]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.247      ; 0.489      ;
; 0.138 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[1]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.249      ; 0.491      ;
; 0.139 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[1]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.247      ; 0.490      ;
; 0.142 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[4]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.472      ;
; 0.143 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[0]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.473      ;
; 0.143 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[7]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.473      ;
; 0.145 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[11]                                                                                    ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.475      ;
; 0.145 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[6]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.225      ; 0.474      ;
; 0.145 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[5]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.249      ; 0.498      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[1]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.476      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[9]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.476      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[12]                                                                                    ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.476      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cs[7]                                                                                                                            ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.223      ; 0.473      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[3]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.472      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[5]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.472      ;
; 0.146 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[5]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.247      ; 0.497      ;
; 0.147 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[7]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.225      ; 0.476      ;
; 0.147 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[2]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.473      ;
; 0.149 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[5]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.479      ;
; 0.150 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[0]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.476      ;
; 0.155 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[2]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.249      ; 0.508      ;
; 0.156 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[3]                                                                                     ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.226      ; 0.486      ;
; 0.156 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_cc_temp[2]                                                                                                                       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.247      ; 0.507      ;
; 0.159 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[4]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.485      ;
; 0.162 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008|rom_add_f[1]                                                                                                                             ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                          ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.222      ; 0.488      ;
; 0.180 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|was_stalled                                                                                         ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|was_stalled                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|empty_dff       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|empty_dff                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|usedw_is_0_dff  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|usedw_is_0_dff                                         ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|dffe_af                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[0] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[0]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[1] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[1]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[2] ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|low_addressa[2]                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[2]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[2]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[3]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[3]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[1]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.181 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl|cnt[0]                                                                                                                                                     ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n|pipe[0][8]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_8_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[12]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[12]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][20]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][20]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][12]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][12]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_2_n|pipe[0][8]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_1_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|rd_ptr_lsb      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|rd_ptr_lsb                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][2]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][2]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_8_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][23]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][23]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][32]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][32]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][21]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|data_int[0]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_6_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][18]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][18]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_6_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[24]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[24]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[14]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[14]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[15]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[15]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[19]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[19]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[22]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[22]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[23]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[23]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.041      ; 0.313      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_10_pp|data_out[0]                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_5_n|pipe[0][10]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[18]                                                                     ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_b[18]                                                                                                                                                                       ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_4_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n|pipe[0][4]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated|dffe3a[3]                                                                      ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|result_a[3]                                                                                                                                                                        ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.041      ; 0.313      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[5]                                                                                                                               ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[6]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.041      ; 0.313      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated|pipeline_dffe[0]                                                                          ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated|pipeline_dffe[0]                                                                                                                 ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[1]                                                                                                                               ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[2]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.041      ; 0.313      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[0]                                                                                                                               ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001|lsfr_reg[1]                                                                                                                                                                      ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.041      ; 0.313      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][11]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][11]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][10]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n|pipe[0][10]                                                                                                                               ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[9]                                                                                                  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[9]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n|data_out[4]                                                                                                  ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add|res[4]                                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][7]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][7]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][3]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][3]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][2]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][2]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_10_pp|data_out[0]                                                                                              ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_5_n|pipe[0][10]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][8]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n|pipe[0][8]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][1]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][1]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n|pipe[0][0]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][1]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n|pipe[0][1]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_6_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_3_n|pipe[0][6]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][2]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][2]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][1]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][1]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_4_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_2_n|pipe[0][4]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_0_n|pipe[0][0]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n|pipe[0][0]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][24]                                                                                        ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source|data_int[3]                                                                                                                                ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_6_n|pipe[0][13]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_3_n|pipe[0][13]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_6_n|pipe[0][12]                                                                                      ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_3_n|pipe[0][12]                                                                                                                             ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_2_n|pipe[0][9]                                                                                       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_1_n|pipe[0][9]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
; 0.188 ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_4_pp|data_out[0]                                                                                               ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_2_n|pipe[0][4]                                                                                                                              ; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                   ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                 ; To Node                                                                   ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.181 ; sld_hub:auto_hub|tdo                                                      ; sld_hub:auto_hub|tdo                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.307      ;
; 0.189 ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.314      ;
; 0.193 ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.318      ;
; 0.194 ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.319      ;
; 0.195 ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.320      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.214 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.002      ; 1.300      ;
; 0.262 ; sld_hub:auto_hub|jtag_ir_reg[9]                                           ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.387      ;
; 0.263 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.389      ;
; 0.263 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.389      ;
; 0.264 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.390      ;
; 0.267 ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.392      ;
; 0.268 ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.393      ;
; 0.276 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.402      ;
; 0.300 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.001      ; 1.385      ;
; 0.300 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.001      ; 1.385      ;
; 0.300 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.001      ; 1.385      ;
; 0.300 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.001      ; 1.385      ;
; 0.300 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 1.001      ; 1.385      ;
; 0.340 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.466      ;
; 0.341 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.467      ;
; 0.342 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.468      ;
; 0.345 ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.470      ;
; 0.358 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.483      ;
; 0.361 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.486      ;
; 0.399 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.525      ;
; 0.401 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.527      ;
; 0.404 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[14]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.529      ;
; 0.410 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.537      ;
; 0.414 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.540      ;
; 0.414 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.540      ;
; 0.414 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.540      ;
; 0.415 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.541      ;
; 0.427 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.552      ;
; 0.431 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.556      ;
; 0.435 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.562      ;
; 0.437 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.564      ;
; 0.440 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.566      ;
; 0.441 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[4]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.566      ;
; 0.442 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|irsr_reg[1]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.567      ;
; 0.442 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|irf_reg[1][2]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.566      ;
; 0.445 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.572      ;
; 0.445 ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.570      ;
; 0.467 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[12]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.592      ;
; 0.475 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.601      ;
; 0.481 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[13]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.606      ;
; 0.493 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.618      ;
; 0.494 ; sld_hub:auto_hub|hub_mode_reg[1]                                          ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.620      ;
; 0.495 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.619      ;
; 0.503 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|irsr_reg[0]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.503 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.503 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.503 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.503 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.503 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.503 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.628      ;
; 0.505 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.632      ;
; 0.506 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|virtual_ir_scan_reg                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.630      ;
; 0.509 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.636      ;
; 0.510 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.635      ;
; 0.524 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[9]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.650      ;
; 0.526 ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ; sld_hub:auto_hub|virtual_dr_scan_reg                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.650      ;
; 0.527 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.653      ;
; 0.534 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.660      ;
; 0.540 ; sld_hub:auto_hub|tdo_bypass_reg                                           ; sld_hub:auto_hub|tdo_bypass_reg                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.665      ;
; 0.544 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.670      ;
; 0.546 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.673      ;
; 0.548 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.675      ;
; 0.550 ; sld_hub:auto_hub|irsr_reg[1]                                              ; sld_hub:auto_hub|irf_reg[1][1]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.674      ;
; 0.557 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.684      ;
; 0.557 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[5]                       ; sld_hub:auto_hub|reset_ena_reg                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.676      ;
; 0.558 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.043      ; 0.685      ;
; 0.565 ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; sld_hub:auto_hub|irf_reg[1][0]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.690      ;
; 0.567 ; sld_hub:auto_hub|irsr_reg[2]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.691      ;
; 0.572 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.698      ;
; 0.574 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.700      ;
; 0.585 ; sld_hub:auto_hub|irf_reg[1][2]                                            ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.710      ;
; 0.593 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[6]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[6]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.718      ;
; 0.603 ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ; sld_hub:auto_hub|irf_reg[1][2]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.728      ;
; 0.604 ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ; sld_hub:auto_hub|irf_reg[1][1]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.729      ;
; 0.608 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[2]                       ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.039      ; 0.731      ;
; 0.611 ; sld_hub:auto_hub|irsr_reg[3]                                              ; sld_hub:auto_hub|irf_reg[1][3]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.736      ;
; 0.612 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                       ; sld_hub:auto_hub|irsr_reg[4]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.033      ; 0.729      ;
; 0.614 ; sld_hub:auto_hub|irsr_reg[0]                                              ; sld_hub:auto_hub|irf_reg[1][0]                                            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.738      ;
; 0.620 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[10]                      ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[11]                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.745      ;
; 0.631 ; sld_hub:auto_hub|irsr_reg[0]                                              ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.755      ;
; 0.631 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[3]                       ; sld_hub:auto_hub|irsr_reg[3]                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.757      ;
; 0.637 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.763      ;
; 0.642 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 0.777      ;
; 0.646 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                     ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 0.781      ;
; 0.652 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.777      ;
; 0.652 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.777      ;
; 0.652 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[4]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.777      ;
; 0.652 ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[3]                  ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[2]                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.777      ;
+-------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                            ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                                  ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 46.617 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.321      ; 6.691      ;
; 46.617 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.321      ; 6.691      ;
; 46.617 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.321      ; 6.691      ;
; 46.617 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.321      ; 6.691      ;
; 46.617 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.321      ; 6.691      ;
; 46.715 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.322      ; 6.594      ;
; 46.715 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.322      ; 6.594      ;
; 46.715 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.322      ; 6.594      ;
; 46.715 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.322      ; 6.594      ;
; 48.706 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 3.324      ; 4.605      ;
; 49.216 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]    ; sld_hub:auto_hub|tdo                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.020      ; 0.791      ;
; 94.544 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.323     ; 4.120      ;
; 94.544 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.323     ; 4.120      ;
; 94.544 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.323     ; 4.120      ;
; 94.544 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.323     ; 4.120      ;
; 94.544 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.323     ; 4.120      ;
; 94.642 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.322     ; 4.023      ;
; 94.642 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.322     ; 4.023      ;
; 94.642 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.322     ; 4.023      ;
; 94.642 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -1.322     ; 4.023      ;
; 97.242 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.321      ; 6.066      ;
; 97.242 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.321      ; 6.066      ;
; 97.242 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.321      ; 6.066      ;
; 97.242 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.321      ; 6.066      ;
; 97.242 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.321      ; 6.066      ;
; 97.337 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.322      ; 5.972      ;
; 97.337 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.322      ; 5.972      ;
; 97.337 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.322      ; 5.972      ;
; 97.337 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.322      ; 5.972      ;
; 98.846 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.100      ;
; 98.966 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[3]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.979      ;
; 98.986 ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; sld_hub:auto_hub|hub_mode_reg[2]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.050     ; 0.951      ;
; 99.004 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[4]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.051     ; 0.932      ;
; 99.004 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.051     ; 0.932      ;
; 99.009 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; 3.324      ; 4.302      ;
; 99.035 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.043     ; 0.909      ;
; 99.035 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.040     ; 0.912      ;
; 99.109 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.836      ;
; 99.109 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.836      ;
; 99.109 ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.836      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_dr_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.156 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 0.789      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[8]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[7]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[9]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[6]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[2]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[5]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[4]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.211 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[3]                                          ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.735      ;
; 99.259 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[0]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.687      ;
; 99.259 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[1]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.687      ;
; 99.259 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[2]                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.687      ;
; 99.259 ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[0]                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 0.687      ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                             ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                              ; To Node                                                                  ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; -0.992 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.269      ; 3.361      ;
; 0.489  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[0]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.614      ;
; 0.489  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[1]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.614      ;
; 0.489  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[2]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.614      ;
; 0.489  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[0]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.614      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[1]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[8]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[7]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[9]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[6]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[2]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[5]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[4]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.502  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[3]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.041      ; 0.627      ;
; 0.560  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_ir_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.684      ;
; 0.560  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|virtual_dr_scan_reg                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.684      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][0]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][1]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][2]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irf_reg[1][3]                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.574  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.698      ;
; 0.586  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.267      ; 4.937      ;
; 0.586  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.267      ; 4.937      ;
; 0.586  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.267      ; 4.937      ;
; 0.586  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.267      ; 4.937      ;
; 0.634  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.760      ;
; 0.634  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.760      ;
; 0.634  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.760      ;
; 0.660  ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[0]    ; sld_hub:auto_hub|jtag_ir_reg[0]                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.042      ; 0.786      ;
; 0.678  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.266      ; 5.028      ;
; 0.678  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.266      ; 5.028      ;
; 0.678  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.266      ; 5.028      ;
; 0.678  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.266      ; 5.028      ;
; 0.678  ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 4.266      ; 5.028      ;
; 0.679  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|hub_mode_reg[1]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.039      ; 0.802      ;
; 0.703  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; sld_hub:auto_hub|hub_mode_reg[2]                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.032      ; 0.819      ;
; 0.703  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[4]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.031      ; 0.818      ;
; 0.703  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|node_ena[1]~reg0                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.031      ; 0.818      ;
; 0.728  ; sld_hub:auto_hub|clr_reg                               ; sld_hub:auto_hub|irsr_reg[3]                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.852      ;
; 0.851  ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.044      ; 0.979      ;
; 3.546  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.192     ; 3.438      ;
; 3.546  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.192     ; 3.438      ;
; 3.546  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.192     ; 3.438      ;
; 3.546  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.192     ; 3.438      ;
; 3.638  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.193     ; 3.529      ;
; 3.638  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.193     ; 3.529      ;
; 3.638  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.193     ; 3.529      ;
; 3.638  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.193     ; 3.529      ;
; 3.638  ; sld_hub:auto_hub|virtual_ir_scan_reg                   ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; -0.193     ; 3.529      ;
; 49.289 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                      ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.269      ; 3.662      ;
; 50.480 ; sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm|state[8]    ; sld_hub:auto_hub|tdo                                                     ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.116      ; 0.700      ;
; 51.166 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.267      ; 5.537      ;
; 51.166 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.267      ; 5.537      ;
; 51.166 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.267      ; 5.537      ;
; 51.166 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.267      ; 5.537      ;
; 51.260 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.266      ; 5.630      ;
; 51.260 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.266      ; 5.630      ;
; 51.260 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.266      ; 5.630      ;
; 51.260 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.266      ; 5.630      ;
; 51.260 ; altera_reserved_tck                                    ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 4.266      ; 5.630      ;
+--------+--------------------------------------------------------+--------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'U1|pll_100|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                                                                       ;
+-------+--------------+----------------+------------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                  ; Clock Edge ; Target                                                                                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3.753 ; 3.983        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|ram_block1a0~porta_address_reg0                                                                           ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_address_reg0 ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_we_reg       ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[0]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[10]                                                                                                   ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[11]                                                                                                   ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[12]                                                                                                   ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[1]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[2]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[3]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[4]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[5]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[6]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[7]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[8]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated|q_a[9]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[0]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[10]                                                                                                   ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[11]                                                                                                   ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[12]                                                                                                   ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[1]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[2]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[3]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[4]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[5]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[6]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[7]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[8]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated|q_a[9]                                                                                                    ;
; 3.754 ; 3.984        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_address_reg0                                                                         ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[0]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[10]                                                                                                 ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[11]                                                                                                 ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[12]                                                                                                 ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[1]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[2]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[3]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[4]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[5]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[6]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[7]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[8]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_a[9]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[0]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[10]                                                                                                 ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[11]                                                                                                 ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[12]                                                                                                 ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[1]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[2]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[3]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[4]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[5]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[6]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[7]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[8]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|q_b[9]                                                                                                  ;
; 3.755 ; 3.985        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_address_reg0                                                                         ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[0]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[10]                         ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[11]                         ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[12]                         ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[1]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[2]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[3]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[4]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[5]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[6]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[7]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[8]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[9]                          ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~porta_datain_reg0  ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|ram_block1a0~portb_address_reg0 ;
; 3.756 ; 3.986        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~porta_datain_reg0                                                                          ;
; 3.757 ; 3.987        ; 0.230          ; Low Pulse Width  ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated|ram_block1a0~portb_datain_reg0                                                                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[0]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[10]                         ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[11]                         ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[12]                         ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[1]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[2]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[3]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[4]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[5]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[6]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[7]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[8]                          ;
; 3.778 ; 4.008        ; 0.230          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram|q_b[9]                          ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl|sink_stall_reg                                                                                                                       ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[0]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[10]                                                                                                                            ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[11]                                                                                                                            ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[12]                                                                                                                            ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[1]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[2]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[3]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[4]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[5]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[6]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[7]                                                                                                                             ;
; 3.779 ; 3.995        ; 0.216          ; High Pulse Width ; U1|pll_100|altpll_component|pll|clk[0] ; Rise       ; DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|at_sink_data_int[8]                                                                                                                             ;
+-------+--------------+----------------+------------------+----------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                 ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                           ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+
; 9.400  ; 9.400        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0]           ;
; 9.400  ; 9.400        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[1]           ;
; 9.400  ; 9.400        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|observablevcoout ;
; 9.448  ; 9.448        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                 ;
; 9.451  ; 9.451        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|inclk[0]         ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|i                                 ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50~input|i                                 ;
; 10.549 ; 10.549       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|inclk[0]         ;
; 10.552 ; 10.552       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                 ;
; 10.599 ; 10.599       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0]           ;
; 10.599 ; 10.599       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|clk[1]           ;
; 10.599 ; 10.599       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; U1|pll_100|altpll_component|pll|observablevcoout ;
; 16.000 ; 20.000       ; 4.000          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                         ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------+


+-----------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50'                                   ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock     ; Clock Edge ; Target    ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000       ; 4.000          ; Port Rate ; CLOCK2_50 ; Rise       ; CLOCK2_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+


+-----------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50'                                   ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock     ; Clock Edge ; Target    ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000       ; 4.000          ; Port Rate ; CLOCK3_50 ; Rise       ; CLOCK3_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                          ;
+--------+--------------+----------------+------------------+---------------------+------------+---------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                    ;
+--------+--------------+----------------+------------------+---------------------+------------+---------------------------------------------------------------------------+
; 29.420 ; 49.620       ; 20.200         ; High Pulse Width ; altera_reserved_tck ; Fall       ; altera_internal_jtag~SHIFTUSER                                            ;
; 30.180 ; 50.380       ; 20.200         ; Low Pulse Width  ; altera_reserved_tck ; Fall       ; altera_internal_jtag~SHIFTUSER                                            ;
; 49.521 ; 49.705       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0]                    ;
; 49.521 ; 49.705       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                    ;
; 49.521 ; 49.705       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                    ;
; 49.521 ; 49.705       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3]                    ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967                       ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[0]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[10] ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[11] ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[12] ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[1]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[2]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[3]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[4]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[5]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[6]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[7]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[8]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|PZMU7345:HHRH5434|ATKJ2101[9]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[1]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[2]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[3]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[0]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[1]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[2]  ;
; 49.547 ; 49.731       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]  ;
; 49.620 ; 49.620       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag|clkdruser                                            ;
; 49.620 ; 49.620       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag|tck                                                  ;
; 49.620 ; 49.620       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag|tckutap                                              ;
; 49.620 ; 49.620       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag|updateuser                                           ;
; 49.620 ; 49.620       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_reserved_tck~input|o                                               ;
; 49.699 ; 49.699       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|XWDE0671[0]|clk                                   ;
; 49.699 ; 49.699       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|XWDE0671[1]|clk                                   ;
; 49.699 ; 49.699       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|XWDE0671[2]|clk                                   ;
; 49.699 ; 49.699       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|XWDE0671[3]|clk                                   ;
; 49.714 ; 49.714       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~UPDATEUSERclkctrl|inclk[0]                           ;
; 49.714 ; 49.714       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~UPDATEUSERclkctrl|outclk                             ;
; 49.717 ; 49.933       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|tdo                                                      ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|FNUJ6967|clk                                      ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[0]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[10]|clk                         ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[11]|clk                         ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[12]|clk                         ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[1]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[2]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[3]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[4]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[5]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[6]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[7]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[8]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|HHRH5434|ATKJ2101[9]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|AJQN5180[0]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|AJQN5180[1]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|AJQN5180[2]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|AJQN5180[3]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|AJQN5180[4]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|DJFL8584[0]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|DJFL8584[1]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|DJFL8584[2]|clk                          ;
; 49.725 ; 49.725       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; nabboc|pzdyqx_impl_inst|JDCF0099|DJFL8584[3]|clk                          ;
; 49.740 ; 49.740       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~CLKDRUSERclkctrl|inclk[0]                            ;
; 49.740 ; 49.740       ; 0.000          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; altera_internal_jtag~CLKDRUSERclkctrl|outclk                              ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|clr_reg                                                  ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[0]                                          ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[1]                                          ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|hub_mode_reg[2]                                          ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][0]                                            ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][1]                                            ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][2]                                            ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irf_reg[1][3]                                            ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[0]                                              ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[1]                                              ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[2]                                              ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[3]                                              ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|irsr_reg[4]                                              ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[0]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[1]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[2]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[3]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[4]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[5]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[6]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[7]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[8]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|jtag_ir_reg[9]                                           ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|node_ena[1]~reg0                                         ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|reset_ena_reg                                            ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][0]                                     ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][1]                                     ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][2]                                     ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|shadow_irf_reg[1][3]                                     ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[0]                       ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]                       ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|WORD_SR[3]                       ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[0]                  ;
; 49.761 ; 49.945       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_rom_sr:hub_info_reg|word_counter[1]                  ;
+--------+--------------+----------------+------------------+---------------------+------------+---------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------+
; Setup Times                                                                                    ;
+---------------------+---------------------+--------+--------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+--------+--------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; -0.665 ; -0.268 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 0.795  ; 1.020  ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+--------+--------+------------+---------------------+


+----------------------------------------------------------------------------------------------+
; Hold Times                                                                                   ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 3.056 ; 2.807 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 2.505 ; 2.161 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                           ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 1.451 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 1.461 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 4.859 ; 5.321 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 3.530 ; 3.826 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 2.867 ; 3.076 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 3.957 ; 4.275 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 4.313 ; 4.731 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 3.268 ; 3.512 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 3.839 ; 4.172 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 3.869 ; 4.191 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 4.859 ; 5.321 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 3.129 ; 3.367 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 3.786 ; 4.089 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 3.953 ; 4.299 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 3.821 ; 4.115 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 3.435 ; 3.191 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 4.540 ; 4.970 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 3.291 ; 3.545 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 2.897 ; 3.117 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 3.539 ; 3.813 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 4.117 ; 4.512 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 3.122 ; 3.344 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 3.673 ; 3.994 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 3.558 ; 3.846 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 4.540 ; 4.970 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 3.116 ; 3.354 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 3.842 ; 4.168 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 3.974 ; 4.336 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 3.832 ; 4.138 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 2.972 ; 2.785 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 1.442 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 1.435 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;       ; 1.503 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;       ; 1.513 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;       ; 1.493 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;       ; 1.485 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 1.453 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 1.443 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;       ; 1.503 ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;       ; 1.493 ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 9.010 ; 9.437 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                   ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 1.167 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 1.177 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 2.523 ; 2.725 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 3.160 ; 3.445 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 2.523 ; 2.725 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 3.570 ; 3.876 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 3.912 ; 4.314 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 2.908 ; 3.142 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 3.456 ; 3.776 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 3.485 ; 3.795 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 4.435 ; 4.880 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 2.774 ; 3.003 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 3.404 ; 3.697 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 3.565 ; 3.898 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 3.438 ; 3.721 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 3.067 ; 2.832 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 2.551 ; 2.442 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 2.928 ; 3.174 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 2.551 ; 2.763 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 3.168 ; 3.432 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 3.724 ; 4.104 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 2.768 ; 2.982 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 3.296 ; 3.606 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 3.184 ; 3.462 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 4.128 ; 4.541 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 2.761 ; 2.990 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 3.458 ; 3.772 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 3.584 ; 3.933 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 3.448 ; 3.743 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 2.623 ; 2.442 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 1.158 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 1.151 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;       ; 1.217 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;       ; 1.227 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;       ; 1.207 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;       ; 1.200 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 1.170 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 1.160 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;       ; 1.218 ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;       ; 1.208 ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 7.725 ; 8.154 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                 ;
+-----------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                   ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+-----------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                        ; 2.652  ; 0.130 ; 43.466   ; -2.424  ; 3.000               ;
;  CLOCK2_50                              ; N/A    ; N/A   ; N/A      ; N/A     ; 16.000              ;
;  CLOCK3_50                              ; N/A    ; N/A   ; N/A      ; N/A     ; 16.000              ;
;  CLOCK_50                               ; N/A    ; N/A   ; N/A      ; N/A     ; 9.400               ;
;  U1|pll_100|altpll_component|pll|clk[0] ; 2.652  ; 0.130 ; N/A      ; N/A     ; 3.000               ;
;  altera_reserved_tck                    ; 43.900 ; 0.181 ; 43.466   ; -2.424  ; 29.350              ;
; Design-wide TNS                         ; 0.0    ; 0.0   ; 0.0      ; -2.424  ; 0.0                 ;
;  CLOCK2_50                              ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  CLOCK3_50                              ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  CLOCK_50                               ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  U1|pll_100|altpll_component|pll|clk[0] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  altera_reserved_tck                    ; 0.000  ; 0.000 ; 0.000    ; -2.424  ; 0.000               ;
+-----------------------------------------+--------+-------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------+
; Setup Times                                                                                  ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 0.588 ; 0.558 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 3.733 ; 4.244 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+----------------------------------------------------------------------------------------------+
; Hold Times                                                                                   ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference     ;
+---------------------+---------------------+-------+-------+------------+---------------------+
; altera_reserved_tdi ; altera_reserved_tck ; 5.533 ; 5.312 ; Rise       ; altera_reserved_tck ;
; altera_reserved_tms ; altera_reserved_tck ; 3.996 ; 3.754 ; Rise       ; altera_reserved_tck ;
+---------------------+---------------------+-------+-------+------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                             ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 3.199  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 3.209  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 11.128 ; 10.808 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 8.039  ; 7.934  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 6.385  ; 6.370  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 9.224  ; 8.792  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 9.789  ; 9.602  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 7.497  ; 7.294  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 8.668  ; 8.528  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 8.754  ; 8.529  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 11.128 ; 10.808 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 7.055  ; 6.980  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 8.660  ; 8.396  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 9.114  ; 8.866  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 8.823  ; 8.466  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 7.210  ; 7.318  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 10.421 ; 10.126 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 7.531  ; 7.388  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 6.537  ; 6.527  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 8.219  ; 7.901  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 9.346  ; 9.187  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 7.119  ; 6.961  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 8.262  ; 8.173  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 8.072  ; 7.875  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 10.421 ; 10.126 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 7.038  ; 6.964  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 8.787  ; 8.593  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 9.136  ; 8.951  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 8.836  ; 8.532  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 6.303  ; 6.413  ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 3.190  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 3.182  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;        ; 3.122  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;        ; 3.132  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;        ; 3.111  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;        ; 3.104  ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 3.206  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 3.196  ;        ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;        ; 3.128  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;        ; 3.118  ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 19.102 ; 19.794 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+--------+--------+------------+----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                   ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                        ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+
; DAC_CLK_A           ; CLOCK_50            ; 1.167 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ; 1.177 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DA[*]           ; CLOCK_50            ; 2.523 ; 2.725 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[0]          ; CLOCK_50            ; 3.160 ; 3.445 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[1]          ; CLOCK_50            ; 2.523 ; 2.725 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[2]          ; CLOCK_50            ; 3.570 ; 3.876 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[3]          ; CLOCK_50            ; 3.912 ; 4.314 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[4]          ; CLOCK_50            ; 2.908 ; 3.142 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[5]          ; CLOCK_50            ; 3.456 ; 3.776 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[6]          ; CLOCK_50            ; 3.485 ; 3.795 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[7]          ; CLOCK_50            ; 4.435 ; 4.880 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[8]          ; CLOCK_50            ; 2.774 ; 3.003 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[9]          ; CLOCK_50            ; 3.404 ; 3.697 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[10]         ; CLOCK_50            ; 3.565 ; 3.898 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[11]         ; CLOCK_50            ; 3.438 ; 3.721 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DA[12]         ; CLOCK_50            ; 3.067 ; 2.832 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_DB[*]           ; CLOCK_50            ; 2.551 ; 2.442 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[0]          ; CLOCK_50            ; 2.928 ; 3.174 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[1]          ; CLOCK_50            ; 2.551 ; 2.763 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[2]          ; CLOCK_50            ; 3.168 ; 3.432 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[3]          ; CLOCK_50            ; 3.724 ; 4.104 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[4]          ; CLOCK_50            ; 2.768 ; 2.982 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[5]          ; CLOCK_50            ; 3.296 ; 3.606 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[6]          ; CLOCK_50            ; 3.184 ; 3.462 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[7]          ; CLOCK_50            ; 4.128 ; 4.541 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[8]          ; CLOCK_50            ; 2.761 ; 2.990 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[9]          ; CLOCK_50            ; 3.458 ; 3.772 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[10]         ; CLOCK_50            ; 3.584 ; 3.933 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[11]         ; CLOCK_50            ; 3.448 ; 3.743 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
;  DAC_DB[12]         ; CLOCK_50            ; 2.623 ; 2.442 ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ; 1.158 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ; 1.151 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_A           ; CLOCK_50            ;       ; 1.217 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_CLK_B           ; CLOCK_50            ;       ; 1.227 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_A           ; CLOCK_50            ;       ; 1.207 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; DAC_WRT_B           ; CLOCK_50            ;       ; 1.200 ; Fall       ; U1|pll_100|altpll_component|pll|clk[0] ;
; ADC_CLK_A           ; CLOCK_50            ; 1.170 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ; 1.160 ;       ; Rise       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_A           ; CLOCK_50            ;       ; 1.218 ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; ADC_CLK_B           ; CLOCK_50            ;       ; 1.208 ; Fall       ; U1|pll_100|altpll_component|pll|clk[1] ;
; altera_reserved_tdo ; altera_reserved_tck ; 7.725 ; 8.154 ; Fall       ; altera_reserved_tck                    ;
+---------------------+---------------------+-------+-------+------------+----------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin                 ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ADC_CLK_A           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ADC_CLK_B           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ADC_OEB_A           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ADC_OEB_B           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_CLK_A           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_CLK_B           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[0]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[1]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[2]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[3]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[4]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[5]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[6]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[7]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[8]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[9]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[10]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[11]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[12]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DA[13]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[0]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[1]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[2]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[3]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[4]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[5]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[6]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[7]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[8]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[9]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[10]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[11]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[12]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_DB[13]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_MODE            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_WRT_A           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; DAC_WRT_B           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; altera_reserved_tdo ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; CLOCK2_50               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK3_50               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ADC_DA[0]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[1]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[2]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[3]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[4]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[5]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[6]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[7]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[8]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[9]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[10]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[11]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[12]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DA[13]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[0]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[1]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[2]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[3]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[4]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[5]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[6]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[7]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[8]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[9]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[10]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[11]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[12]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_DB[13]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_OTR_A               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ADC_OTR_B               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; OSC_SMA_ADC4            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; SMA_DAC4                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; I2C_SDAT                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tms     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; altera_reserved_tck     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; altera_reserved_tdi     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; ADC_CLK_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; ADC_CLK_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; ADC_OEB_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; ADC_OEB_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CLK_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CLK_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[0]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[1]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[2]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[3]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[7]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[8]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[9]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[10]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[11]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[12]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[13]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[0]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[1]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[2]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[3]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[7]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[8]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[9]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[10]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[11]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[12]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[13]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_MODE            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_WRT_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; DAC_WRT_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.07e-09 V                   ; 2.36 V              ; -0.00737 V          ; 0.209 V                              ; 0.012 V                              ; 5.22e-10 s                  ; 5.33e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.07e-09 V                  ; 2.36 V             ; -0.00737 V         ; 0.209 V                             ; 0.012 V                             ; 5.22e-10 s                 ; 5.33e-10 s                 ; Yes                       ; Yes                       ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; altera_reserved_tdo ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.3e-08 V                    ; 2.33 V              ; -0.0041 V           ; 0.049 V                              ; 0.077 V                              ; 9.24e-10 s                  ; 2.03e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.3e-08 V                   ; 2.33 V             ; -0.0041 V          ; 0.049 V                             ; 0.077 V                             ; 9.24e-10 s                 ; 2.03e-09 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.74e-09 V                   ; 2.37 V              ; -0.0346 V           ; 0.198 V                              ; 0.094 V                              ; 3.14e-10 s                  ; 2.92e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.74e-09 V                  ; 2.37 V             ; -0.0346 V          ; 0.198 V                             ; 0.094 V                             ; 3.14e-10 s                 ; 2.92e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.57e-09 V                   ; 2.37 V              ; -0.00683 V          ; 0.171 V                              ; 0.018 V                              ; 4.97e-10 s                  ; 6.66e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.57e-09 V                  ; 2.37 V             ; -0.00683 V         ; 0.171 V                             ; 0.018 V                             ; 4.97e-10 s                 ; 6.66e-10 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; ADC_CLK_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; ADC_CLK_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; ADC_OEB_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; ADC_OEB_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CLK_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_CLK_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[0]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[1]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[2]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[3]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[7]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[8]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[9]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[10]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[11]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[12]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DA[13]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[0]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[1]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[2]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[3]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[7]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[8]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[9]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[10]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[11]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[12]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_DB[13]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_MODE            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_WRT_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; DAC_WRT_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.93e-07 V                   ; 2.34 V              ; -0.00869 V          ; 0.14 V                               ; 0.046 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.93e-07 V                  ; 2.34 V             ; -0.00869 V         ; 0.14 V                              ; 0.046 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; altera_reserved_tdo ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.29e-06 V                   ; 2.33 V              ; 1.29e-06 V          ; 0.018 V                              ; 0.046 V                              ; 1.15e-09 s                  ; 2.62e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.29e-06 V                  ; 2.33 V             ; 1.29e-06 V         ; 0.018 V                             ; 0.046 V                             ; 1.15e-09 s                 ; 2.62e-09 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.55e-07 V                   ; 2.35 V              ; -0.00259 V          ; 0.097 V                              ; 0.005 V                              ; 4.49e-10 s                  ; 3.86e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.55e-07 V                  ; 2.35 V             ; -0.00259 V         ; 0.097 V                             ; 0.005 V                             ; 4.49e-10 s                 ; 3.86e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.54e-07 V                   ; 2.34 V              ; -0.00774 V          ; 0.109 V                              ; 0.026 V                              ; 6.58e-10 s                  ; 8.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.54e-07 V                  ; 2.34 V             ; -0.00774 V         ; 0.109 V                             ; 0.026 V                             ; 6.58e-10 s                 ; 8.24e-10 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; I2C_SCLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; ADC_CLK_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; ADC_CLK_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; ADC_OEB_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; ADC_OEB_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_CLK_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_CLK_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[0]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[1]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[2]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[3]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[7]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[8]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[9]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[10]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[11]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[12]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DA[13]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[0]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[1]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[2]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[3]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[7]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[8]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[9]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[10]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[11]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[12]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_DB[13]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_MODE            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_WRT_A           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; DAC_WRT_B           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.71 V              ; -0.0317 V           ; 0.148 V                              ; 0.064 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.71 V             ; -0.0317 V          ; 0.148 V                             ; 0.064 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; I2C_SDAT            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; altera_reserved_tdo ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 1.77e-07 V                   ; 2.65 V              ; -0.0108 V           ; 0.18 V                               ; 0.17 V                               ; 6.63e-10 s                  ; 1.56e-09 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 1.77e-07 V                  ; 2.65 V             ; -0.0108 V          ; 0.18 V                              ; 0.17 V                              ; 6.63e-10 s                 ; 1.56e-09 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.74 V              ; -0.06 V             ; 0.158 V                              ; 0.08 V                               ; 2.68e-10 s                  ; 2.19e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.74 V             ; -0.06 V            ; 0.158 V                             ; 0.08 V                              ; 2.68e-10 s                 ; 2.19e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.54e-08 V                   ; 2.7 V               ; -0.00943 V          ; 0.276 V                              ; 0.035 V                              ; 3.19e-10 s                  ; 4.99e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.54e-08 V                  ; 2.7 V              ; -0.00943 V         ; 0.276 V                             ; 0.035 V                             ; 3.19e-10 s                 ; 4.99e-10 s                 ; No                        ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                             ;
+----------------------------------------+----------------------------------------+----------+----------+----------+----------+
; From Clock                             ; To Clock                               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------+----------------------------------------+----------+----------+----------+----------+
; altera_reserved_tck                    ; altera_reserved_tck                    ; 520      ; 22       ; 23       ; 1        ;
; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 45687    ; 0        ; 0        ; 0        ;
+----------------------------------------+----------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                              ;
+----------------------------------------+----------------------------------------+----------+----------+----------+----------+
; From Clock                             ; To Clock                               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------+----------------------------------------+----------+----------+----------+----------+
; altera_reserved_tck                    ; altera_reserved_tck                    ; 520      ; 22       ; 23       ; 1        ;
; U1|pll_100|altpll_component|pll|clk[0] ; U1|pll_100|altpll_component|pll|clk[0] ; 45687    ; 0        ; 0        ; 0        ;
+----------------------------------------+----------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------+
; Recovery Transfers                                                                    ;
+---------------------+---------------------+----------+----------+----------+----------+
; From Clock          ; To Clock            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------+---------------------+----------+----------+----------+----------+
; altera_reserved_tck ; altera_reserved_tck ; 52       ; 10       ; 1        ; 0        ;
+---------------------+---------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------+
; Removal Transfers                                                                     ;
+---------------------+---------------------+----------+----------+----------+----------+
; From Clock          ; To Clock            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+---------------------+---------------------+----------+----------+----------+----------+
; altera_reserved_tck ; altera_reserved_tck ; 52       ; 10       ; 1        ; 0        ;
+---------------------+---------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 2     ; 2    ;
; Unconstrained Input Port Paths  ; 38    ; 38   ;
; Unconstrained Output Ports      ; 33    ; 33   ;
; Unconstrained Output Port Paths ; 33    ; 33   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Jun 17 21:14:19 2011
Info: Command: quartus_sta DE2_115_ADDA -c DE2_115_ADDA
Info: qsta_default_script.tcl version: #4
Info: Core supply voltage is 1.2V
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Evaluating HDL-embedded SDC commands
    Info: Entity MDCK2395
        Info: set_disable_timing [get_cells -hierarchical LJMV0916_0]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_0]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_1]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_2]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_3]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_4]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_5]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_6]
        Info: set_disable_timing [get_cells -hierarchical EPEO2888_7]
        Info: set_disable_timing [get_cells -hierarchical WCRO7487_0]
    Info: Entity pzdyqx_impl
        Info: set_false_path -from [get_keepers {altera_reserved_tdi}] -to [get_keepers {pzdyqx*}]
    Info: Entity sld_hub
        Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]
        Info: set_clock_groups -asynchronous -group {altera_reserved_tck}
Info: Reading SDC File: 'DE2_115_ADDA.SDC'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {U1|pll_100|altpll_component|pll|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {U1|pll_100|altpll_component|pll|clk[0]} {U1|pll_100|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {U1|pll_100|altpll_component|pll|inclk[0]} -divide_by 4 -multiply_by 5 -duty_cycle 50.00 -name {U1|pll_100|altpll_component|pll|clk[1]} {U1|pll_100|altpll_component|pll|clk[1]}
Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.020
Info: Analyzing Slow 1200mV 85C Model
Info: Worst-case setup slack is 2.652
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     2.652         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:    43.900         0.000 altera_reserved_tck 
Info: Worst-case hold slack is 0.393
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.393         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:     0.441         0.000 altera_reserved_tck 
Info: Worst-case recovery slack is 43.466
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    43.466         0.000 altera_reserved_tck 
Critical Warning: Timing requirements not met
Info: Worst-case removal slack is -2.424
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -2.424        -2.424 altera_reserved_tck 
Info: Worst-case minimum pulse width slack is 3.000
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     3.000         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:     9.891         0.000 CLOCK_50 
    Info:    16.000         0.000 CLOCK2_50 
    Info:    16.000         0.000 CLOCK3_50 
    Info:    29.350         0.000 altera_reserved_tck 
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.020
Info: Worst-case setup slack is 3.055
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     3.055         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:    44.084         0.000 altera_reserved_tck 
Info: Worst-case hold slack is 0.228
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.228         0.000 altera_reserved_tck 
    Info:     0.379         0.000 U1|pll_100|altpll_component|pll|clk[0] 
Info: Worst-case recovery slack is 43.850
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    43.850         0.000 altera_reserved_tck 
Critical Warning: Timing requirements not met
Info: Worst-case removal slack is -2.375
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -2.375        -2.375 altera_reserved_tck 
Info: Worst-case minimum pulse width slack is 3.000
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     3.000         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:     9.882         0.000 CLOCK_50 
    Info:    16.000         0.000 CLOCK2_50 
    Info:    16.000         0.000 CLOCK3_50 
    Info:    29.775         0.000 altera_reserved_tck 
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -rise_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -fall_to [get_clocks {U1|pll_100|altpll_component|pll|clk[0]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.020
Info: Worst-case setup slack is 5.539
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     5.539         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:    47.627         0.000 altera_reserved_tck 
Info: Worst-case hold slack is 0.130
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.130         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:     0.181         0.000 altera_reserved_tck 
Info: Worst-case recovery slack is 46.617
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    46.617         0.000 altera_reserved_tck 
Critical Warning: Timing requirements not met
Info: Worst-case removal slack is -0.992
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -0.992        -0.992 altera_reserved_tck 
Info: Worst-case minimum pulse width slack is 3.753
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     3.753         0.000 U1|pll_100|altpll_component|pll|clk[0] 
    Info:     9.400         0.000 CLOCK_50 
    Info:    16.000         0.000 CLOCK2_50 
    Info:    16.000         0.000 CLOCK3_50 
    Info:    29.420         0.000 altera_reserved_tck 
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 310 megabytes
    Info: Processing ended: Fri Jun 17 21:14:41 2011
    Info: Elapsed time: 00:00:22
    Info: Total CPU time (on all processors): 00:00:19


