--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_A1="DATAA" INPUT_SOURCE_B0="DATAB" INPUT_SOURCE_B1="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_REGISTER="CLOCK0" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" WIDTH_A=13 WIDTH_B=13 WIDTH_RESULT=27 clock0 dataa datab ena0 result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 10.1SP1 cbx_alt_ded_mult_y 2011:01:19:21:13:40:SJ cbx_altmult_add 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_mult 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_padd 2011:01:19:21:13:40:SJ cbx_parallel_add 2011:01:19:21:13:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ  VERSION_END


-- Copyright (C) 1991-2011 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION ded_mult_rj51 (aclr[3..0], clock[3..0], dataa[12..0], datab[12..0], ena[3..0])
RETURNS ( result[25..0]);
FUNCTION soft (in)
RETURNS ( out);

--synthesis_resources = lut 27 reg 27 
OPTIONS ALTERA_INTERNAL_OPTION = "{-to dffe5a} MAX_FANOUT=5";

SUBDESIGN mult_add_gpb2
( 
	clock0	:	input;
	dataa[25..0]	:	input;
	datab[25..0]	:	input;
	ena0	:	input;
	result[26..0]	:	output;
) 
VARIABLE
	add3_result[26..0]	:	WIRE;
	ded_mult1 : ded_mult_rj51;
	ded_mult2 : ded_mult_rj51;
	dffe5a[26..0] : dffe;
	sft4a[26..0] : soft;
	aclr0	: NODE;
	dataa_bus[25..0]	: WIRE;
	datab_bus[25..0]	: WIRE;
	w_input120w[26..0]	: WIRE;
	w_input126w[26..0]	: WIRE;

BEGIN 
	add3_result[] = w_input120w[] + w_input126w[];
	ded_mult1.aclr[] = ( B"000", aclr0);
	ded_mult1.clock[] = ( B"111", clock0);
	ded_mult1.dataa[] = ( dataa_bus[12..0]);
	ded_mult1.datab[] = ( datab_bus[12..0]);
	ded_mult1.ena[] = ( B"111", ena0);
	ded_mult2.aclr[] = ( B"000", aclr0);
	ded_mult2.clock[] = ( B"111", clock0);
	ded_mult2.dataa[] = ( dataa_bus[25..13]);
	ded_mult2.datab[] = ( datab_bus[25..13]);
	ded_mult2.ena[] = ( B"111", ena0);
	dffe5a[].clk = clock0;
	dffe5a[].clrn = (! aclr0);
	dffe5a[].d = sft4a[].out;
	dffe5a[].ena = ena0;
	sft4a[].in = add3_result[];
	aclr0 = GND;
	dataa_bus[] = ( dataa[25..0]);
	datab_bus[] = ( datab[25..0]);
	result[26..0] = dffe5a[26..0].q;
	w_input120w[] = ( ded_mult1.result[25..25], ded_mult1.result[25..0]);
	w_input126w[] = ( ded_mult2.result[25..25], ded_mult2.result[25..0]);
END;
--VALID FILE
