{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 17 20:57:40 2011 " "Info: Processing started: Fri Jun 17 20:57:40 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco91_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco91_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco91_st " "Info: Found entity 1: nco91_st" {  } { { "nco91_st.v" "" { Text "G:/FPGA/DE2_115_ADA/nco91_st.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco91.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco91.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco91 " "Info: Found entity 1: nco91" {  } { { "nco91.v" "" { Text "G:/FPGA/DE2_115_ADA/nco91.v" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_add.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lpm_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add " "Info: Found entity 1: lpm_add" {  } { { "lpm_add.v" "" { Text "G:/FPGA/DE2_115_ADA/lpm_add.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de2_115_adda_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file de2_115_adda_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_115_ADDA_TOP " "Info: Found entity 1: DE2_115_ADDA_TOP" {  } { { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mynco_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mynco_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 mynco_st " "Info: Found entity 1: mynco_st" {  } { { "mynco_st.v" "" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mynco.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mynco.v" { { "Info" "ISGN_ENTITY_NAME" "1 mynco " "Info: Found entity 1: mynco" {  } { { "mynco.v" "" { Text "G:/FPGA/DE2_115_ADA/mynco.v" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ovalid DE2_115_ADDA_TOP.v(101) " "Warning (10236): Verilog HDL Implicit Net warning at DE2_115_ADDA_TOP.v(101): created implicit net for \"ovalid\"" {  } { { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 101 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "de2_115_adda.v 1 1 " "Warning: Using design file de2_115_adda.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_115_ADDA " "Info: Found entity 1: DE2_115_ADDA" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_115_ADDA " "Info: Elaborating entity \"DE2_115_ADDA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "I2C_SCLK de2_115_adda.v(88) " "Warning (10034): Output port \"I2C_SCLK\" at de2_115_adda.v(88) has no driver" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 88 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DE2_115_ADDA_TOP DE2_115_ADDA_TOP:U1 " "Info: Elaborating entity \"DE2_115_ADDA_TOP\" for hierarchy \"DE2_115_ADDA_TOP:U1\"" {  } { { "de2_115_adda.v" "U1" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phasinc2 DE2_115_ADDA_TOP.v(72) " "Warning (10036): Verilog HDL or VHDL warning at DE2_115_ADDA_TOP.v(72): object \"phasinc2\" assigned a value but never read" {  } { { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 72 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll DE2_115_ADDA_TOP:U1\|pll:pll_100 " "Info: Elaborating entity \"pll\" for hierarchy \"DE2_115_ADDA_TOP:U1\|pll:pll_100\"" {  } { { "DE2_115_ADDA_TOP.v" "pll_100" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\"" {  } { { "pll.v" "altpll_component" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\"" {  } { { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Info: Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Info: Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 4 " "Info: Parameter \"clk1_divide_by\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Info: Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Info: Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Info: Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Info: Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Info: Parameter \"intended_device_family\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Info: Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Info: Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Info: Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Info: Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Info: Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_USED " "Info: Parameter \"port_pllena\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Info: Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Info: Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Info: Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Info: Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Info: Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Info: Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mynco DE2_115_ADDA_TOP:U1\|mynco:sin1 " "Info: Elaborating entity \"mynco\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\"" {  } { { "DE2_115_ADDA_TOP.v" "sin1" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 102 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mynco_st DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst " "Info: Elaborating entity \"mynco_st\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\"" {  } { { "mynco.v" "mynco_st_inst" { Text "G:/FPGA/DE2_115_ADA/mynco.v" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "select_s mynco_st.v(88) " "Warning (10036): Verilog HDL or VHDL warning at mynco_st.v(88): object \"select_s\" assigned a value but never read" {  } { { "mynco_st.v" "" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 88 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WCPT_PRELIMINARY_FAMILY_SUPPORT" "\"NCO\" (6AF7_0014) Cyclone IV E " "Warning: Support for IP core \"NCO\" (6AF7_0014) in device family Cyclone IV E is preliminary and specifications are subject to change" {  } {  } 0 0 "Support for IP core %1!s! in device family %2!s! is preliminary and specifications are subject to change" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_altqmcpipe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_altqmcpipe.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_altqmcpipe " "Info: Found entity 1: asj_altqmcpipe" {  } { { "asj_altqmcpipe.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_altqmcpipe.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_altqmcpipe DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000 " "Info: Elaborating entity \"asj_altqmcpipe\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\"" {  } { { "mynco_st.v" "ux000" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 104 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" {  } { { "asj_altqmcpipe.v" "acc" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_altqmcpipe.v" 52 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_v4i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_v4i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_v4i " "Info: Found entity 1: add_sub_v4i" {  } { { "db/add_sub_v4i.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_v4i.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_v4i DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated " "Info: Elaborating entity \"add_sub_v4i\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_dxx_g.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_dxx_g.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_dxx_g " "Info: Found entity 1: asj_dxx_g" {  } { { "asj_dxx_g.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx_g.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_dxx_g DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001 " "Info: Elaborating entity \"asj_dxx_g\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\"" {  } { { "mynco_st.v" "ux001" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 122 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_dxx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_dxx.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_dxx " "Info: Found entity 1: asj_dxx" {  } { { "asj_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_dxx DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002 " "Info: Elaborating entity \"asj_dxx\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\"" {  } { { "mynco_st.v" "ux002" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 131 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\"" {  } { { "asj_dxx.v" "ux014" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\"" {  } { { "asj_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 41 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 21 " "Info: Parameter \"lpm_width\" = \"21\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 41 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qth.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qth.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qth " "Info: Found entity 1: add_sub_qth" {  } { { "db/add_sub_qth.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_qth.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_qth DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated " "Info: Elaborating entity \"add_sub_qth\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_apr_dxx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_apr_dxx.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_apr_dxx " "Info: Found entity 1: asj_nco_apr_dxx" {  } { { "asj_nco_apr_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_apr_dxx.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_apr_dxx DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_apr_dxx:ux0219 " "Info: Elaborating entity \"asj_nco_apr_dxx\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_apr_dxx:ux0219\"" {  } { { "mynco_st.v" "ux0219" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 138 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_gam_dp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_gam_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_gam_dp " "Info: Found entity 1: asj_gam_dp" {  } { { "asj_gam_dp.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_gam_dp.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_gam_dp DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_gam_dp:ux008 " "Info: Elaborating entity \"asj_gam_dp\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_gam_dp:ux008\"" {  } { { "mynco_st.v" "ux008" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 150 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_as_m_dp_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_as_m_dp_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_dp_cen " "Info: Found entity 1: asj_nco_as_m_dp_cen" {  } { { "asj_nco_as_m_dp_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_dp_cen DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220 " "Info: Elaborating entity \"asj_nco_as_m_dp_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\"" {  } { { "mynco_st.v" "ux0220" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 162 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" {  } { { "asj_nco_as_m_dp_cen.v" "altsyncram_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 83 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" {  } { { "asj_nco_as_m_dp_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 83 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 13 " "Info: Parameter \"width_a\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 13 " "Info: Parameter \"width_b\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Info: Parameter \"widthad_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Info: Parameter \"numwords_b\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Info: Parameter \"width_byteena_b\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Info: Parameter \"outdata_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Info: Parameter \"indata_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Info: Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file mynco_sin_c.hex " "Info: Parameter \"init_file\" = \"mynco_sin_c.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CycloneII " "Info: Parameter \"intended_device_family\" = \"CycloneII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_as_m_dp_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 83 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4g72.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4g72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4g72 " "Info: Found entity 1: altsyncram_4g72" {  } { { "db/altsyncram_4g72.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_4g72.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4g72 DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated " "Info: Elaborating entity \"altsyncram_4g72\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_as_m_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_as_m_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_cen " "Info: Found entity 1: asj_nco_as_m_cen" {  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122 " "Info: Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\"" {  } { { "mynco_st.v" "ux0122" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 174 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "altsyncram_component0" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 13 " "Info: Parameter \"width_a\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file mynco_sin_f.hex " "Info: Parameter \"init_file\" = \"mynco_sin_f.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CycloneII " "Info: Parameter \"intended_device_family\" = \"CycloneII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s791.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s791.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s791 " "Info: Found entity 1: altsyncram_s791" {  } { { "db/altsyncram_s791.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_s791.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s791 DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_s791:auto_generated " "Info: Elaborating entity \"altsyncram_s791\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_s791:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123 " "Info: Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\"" {  } { { "mynco_st.v" "ux0123" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 186 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "altsyncram_component0" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 13 " "Info: Parameter \"width_a\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file mynco_cos_f.hex " "Info: Parameter \"init_file\" = \"mynco_cos_f.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CycloneII " "Info: Parameter \"intended_device_family\" = \"CycloneII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_n791.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n791.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_n791 " "Info: Found entity 1: altsyncram_n791" {  } { { "db/altsyncram_n791.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_n791.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_n791 DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_n791:auto_generated " "Info: Elaborating entity \"altsyncram_n791\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_n791:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/mac_i_lpmd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/mac_i_lpmd.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_i_lpmd " "Info: Found entity 1: mac_i_lpmd" {  } { { "mac_i_lpmd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/mac_i_lpmd.v" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_i_lpmd DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0 " "Info: Elaborating entity \"mac_i_lpmd\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\"" {  } { { "mynco_st.v" "m0" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 202 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/lmsd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/lmsd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lmsd " "Info: Found entity 1: lmsd" {  } { { "lmsd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 50 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lmsd DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0 " "Info: Elaborating entity \"lmsd\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\"" {  } { { "mac_i_lpmd.v" "m_0" { Text "G:/FPGA/DE2_115_ADA/nco-library/mac_i_lpmd.v" 59 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\"" {  } { { "lmsd.v" "lpm_mult_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\"" {  } { { "lmsd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 13 " "Info: Parameter \"lpm_widtha\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 13 " "Info: Parameter \"lpm_widthb\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 26 " "Info: Parameter \"lpm_widthp\" = \"26\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 26 " "Info: Parameter \"lpm_widths\" = \"26\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Info: Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=7 " "Info: Parameter \"lpm_hint\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 3 " "Info: Parameter \"lpm_pipeline\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "lmsd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 75 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_7ju.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_7ju.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_7ju " "Info: Found entity 1: mult_7ju" {  } { { "db/mult_7ju.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/mult_7ju.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_7ju DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\|mult_7ju:auto_generated " "Info: Elaborating entity \"mult_7ju\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\|mult_7ju:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/las.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/las.v" { { "Info" "ISGN_ENTITY_NAME" "1 las " "Info: Found entity 1: las" {  } { { "las.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "las DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0 " "Info: Elaborating entity \"las\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\"" {  } { { "mac_i_lpmd.v" "a_0" { Text "G:/FPGA/DE2_115_ADA/nco-library/mac_i_lpmd.v" 82 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "las.v" "lpm_add_sub_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 61 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "las.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 61 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 27 " "Info: Parameter \"lpm_width\" = \"27\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UNUSED " "Info: Parameter \"lpm_direction\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "las.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 61 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_g0j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_g0j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_g0j " "Info: Found entity 1: add_sub_g0j" {  } { { "db/add_sub_g0j.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_g0j.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_g0j DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\|add_sub_g0j:auto_generated " "Info: Elaborating entity \"add_sub_g0j\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\|add_sub_g0j:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_derot.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_derot.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_derot " "Info: Found entity 1: asj_nco_derot" {  } { { "asj_nco_derot.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_derot.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_derot DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_derot:ux0136 " "Info: Elaborating entity \"asj_nco_derot\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_derot:ux0136\"" {  } { { "mynco_st.v" "ux0136" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 215 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_mob_w.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_mob_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mob_w " "Info: Found entity 1: asj_nco_mob_w" {  } { { "asj_nco_mob_w.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_w DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0 " "Info: Elaborating entity \"asj_nco_mob_w\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\"" {  } { { "mynco_st.v" "blk0" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 225 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "asj_nco_mob_w.v" "lpm_add_sub_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "asj_nco_mob_w.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 54 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 13 " "Info: Parameter \"lpm_width\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_mob_w.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 54 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_i7l.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_i7l.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_i7l " "Info: Found entity 1: add_sub_i7l" {  } { { "db/add_sub_i7l.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_i7l.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_i7l DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_i7l:auto_generated " "Info: Elaborating entity \"add_sub_i7l\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_i7l:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_isdr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_isdr.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Info: Found entity 1: asj_nco_isdr" {  } { { "asj_nco_isdr.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr " "Info: Elaborating entity \"asj_nco_isdr\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\"" {  } { { "mynco_st.v" "ux710isdr" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 236 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" {  } { { "asj_nco_isdr.v" "lpm_counter_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 33 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" {  } { { "asj_nco_isdr.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 33 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 4 " "Info: Parameter \"lpm_width\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Info: Parameter \"lpm_type\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Info: Parameter \"lpm_direction\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_isdr.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 33 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ori.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ori.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ori " "Info: Found entity 1: cntr_ori" {  } { { "db/cntr_ori.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cntr_ori.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ori DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated " "Info: Elaborating entity \"cntr_ori\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSHIFT_TAPS_INFERRED" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\|pipeline_dffe\[13\]~0 " "Info: Inferred altshift_taps megafunction from the following design logic: \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\|pipeline_dffe\[13\]~0\"" { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMBER_OF_TAPS 1 " "Info: Parameter NUMBER_OF_TAPS set to 1" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "TAP_DISTANCE 3 " "Info: Parameter TAP_DISTANCE set to 3" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH 14 " "Info: Parameter WIDTH set to 14" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1}  } { { "db/add_sub_qth.tdf" "pipeline_dffe\[13\]~0" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_qth.tdf" 32 15 0 } }  } 0 0 "Inferred altshift_taps megafunction from the following design logic: \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\|altshift_taps:pipeline_dffe_rtl_0 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\|altshift_taps:pipeline_dffe_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\|altshift_taps:pipeline_dffe_rtl_0 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\|altshift_taps:pipeline_dffe_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 1 " "Info: Parameter \"NUMBER_OF_TAPS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 3 " "Info: Parameter \"TAP_DISTANCE\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 14 " "Info: Parameter \"WIDTH\" = \"14\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_a6m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/shift_taps_a6m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_a6m " "Info: Found entity 1: shift_taps_a6m" {  } { { "db/shift_taps_a6m.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/shift_taps_a6m.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vk31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vk31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vk31 " "Info: Found entity 1: altsyncram_vk31" {  } { { "db/altsyncram_vk31.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_vk31.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_24e.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_24e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_24e " "Info: Found entity 1: add_sub_24e" {  } { { "db/add_sub_24e.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_24e.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_6pf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_6pf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_6pf " "Info: Found entity 1: cntr_6pf" {  } { { "db/cntr_6pf.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cntr_6pf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ogc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_ogc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ogc " "Info: Found entity 1: cmpr_ogc" {  } { { "db/cmpr_ogc.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cmpr_ogc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_USE_OPENCORE_PLUS" "" "Warning: OpenCore Plus Hardware Evaluation feature is turned on for the following cores" { { "Warning" "WSGN_FOUND_OCP_CORE" "\"NCO\" (6AF7_0014) " "Warning: \"\"NCO\" (6AF7_0014)\" will use the OpenCore Plus Hardware Evaluation feature" {  } {  } 0 0 "\"%1!s!\" will use the OpenCore Plus Hardware Evaluation feature" 0 0 "" 0 -1}  } {  } 0 0 "OpenCore Plus Hardware Evaluation feature is turned on for the following cores" 0 0 "" 0 -1}
{ "Warning" "WSCI_OPENCORE_USER_MSG_ROOT" "" "Warning: Messages from megafunction that supports OpenCore Plus feature" { { "Warning" "WSCI_OPENCORE_USER_MSG_CORE_ROOT" "NCO MegaCore " "Warning: Messages from megafunction that supports OpenCore Plus feature NCO MegaCore" { { "Warning" "WSCI_OPENCORE_USER_MSG_SUB" "The output signals fsin_o and fcos_o are forced low when the evaluation time expires " "Warning: The output signals fsin_o and fcos_o are forced low when the evaluation time expires" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Messages from megafunction that supports OpenCore Plus feature %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Messages from megafunction that supports OpenCore Plus feature" 0 0 "" 0 -1}
{ "Warning" "WSCI_OPENCORE_HARD_TIMEOUT_INFO" "1 hour " "Warning: Megafunction that supports OpenCore Plus feature will stop functioning in 1 hour after device is programmed" {  } {  } 0 0 "Megafunction that supports OpenCore Plus feature will stop functioning in %1!s! after device is programmed" 0 0 "" 0 -1}
{ "Info" "ISCI_OPENCORE_SOFT_TIMEOUT_INF_INFO" "" "Info: Evaluation period of megafunction that supports OpenCore Plus feature can be extended indefinitely by using tethered operation" {  } {  } 0 0 "Evaluation period of megafunction that supports OpenCore Plus feature can be extended indefinitely by using tethered operation" 0 0 "" 0 -1}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 0 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "Warning: The following bidir pins have no drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "I2C_SDAT " "Warning: Bidir \"I2C_SDAT\" has no driver" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 89 -1 0 } }  } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1}  } {  } 0 0 "The following bidir pins have no drivers" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "I2C_SCLK GND " "Warning (13410): Pin \"I2C_SCLK\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 88 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ADC_OEB_A GND " "Warning (13410): Pin \"ADC_OEB_A\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 96 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ADC_OEB_B GND " "Warning (13410): Pin \"ADC_OEB_B\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 97 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DAC_DA\[13\] GND " "Warning (13410): Pin \"DAC_DA\[13\]\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 102 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DAC_DB\[13\] GND " "Warning (13410): Pin \"DAC_DB\[13\]\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 103 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DAC_MODE VCC " "Warning (13410): Pin \"DAC_MODE\" is stuck at VCC" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 104 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Info: Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "19 19 " "Info: 19 registers lost all their fanouts during netlist optimizations. The first 19 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[3\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[2\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[1\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[0\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[10\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[9\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[8\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[7\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[6\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[5\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[4\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[3\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[2\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[1\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[0\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\|pipeline_dffe\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[3\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[2\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[1\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[0\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\|dxxrv\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "pzdyqx:nabboc " "Info: Timing-Driven Synthesis is running on partition \"pzdyqx:nabboc\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll " "Info: Adding node \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "34 " "Warning: Design contains 34 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK2_50 " "Warning (15610): No output dependent on input pin \"CLOCK2_50\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 84 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK3_50 " "Warning (15610): No output dependent on input pin \"CLOCK3_50\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 85 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[0\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[0\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[1\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[1\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[2\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[2\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[3\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[3\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[4\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[4\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[5\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[5\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[6\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[6\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[7\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[7\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[8\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[8\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[9\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[9\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[10\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[10\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[11\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[11\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[12\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[12\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[13\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[13\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[0\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[0\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[1\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[1\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[2\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[2\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[3\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[3\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[4\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[4\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[5\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[5\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[6\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[6\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[7\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[7\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[8\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[8\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[9\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[9\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[10\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[10\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[11\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[11\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[12\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[12\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[13\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[13\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_OTR_A " "Warning (15610): No output dependent on input pin \"ADC_OTR_A\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 98 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_OTR_B " "Warning (15610): No output dependent on input pin \"ADC_OTR_B\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 99 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "OSC_SMA_ADC4 " "Warning (15610): No output dependent on input pin \"OSC_SMA_ADC4\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 107 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SMA_DAC4 " "Warning (15610): No output dependent on input pin \"SMA_DAC4\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 108 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "554 " "Info: Implemented 554 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "38 " "Info: Implemented 38 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Info: Implemented 39 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "417 " "Info: Implemented 417 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "53 " "Info: Implemented 53 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 57 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 57 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "261 " "Info: Peak virtual memory: 261 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 17 20:57:52 2011 " "Info: Processing ended: Fri Jun 17 20:57:52 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Info: Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 17 20:57:53 2011 " "Info: Processing started: Fri Jun 17 20:57:53 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_115_ADDA EP4CE115F29C8 " "Info: Selected device EP4CE115F29C8 for design \"DE2_115_ADDA\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Info: Core supply voltage is 1.2V" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll Cyclone IV E PLL " "Info: Implemented PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk0 5 2 0 0 " "Info: Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk1 5 4 0 0 " "Info: Implementing clock multiplication of 5, clock division of 4, and phase shift of 0 degrees (0 ps) for DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 917 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Info: Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a0 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a1 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a1\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a2 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a2\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a3 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a3\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a4 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a5 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a5\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a6 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a6\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a7 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a7\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a8 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a8\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a9 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a9\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a10 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a10\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a11 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a11\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a12 " "Info: Atom \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\|ram_block1a12\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "" 0 -1}  } {  } 0 0 "Found following RAM instances in design that are actually implemented as ROM because the write logic is always disabled" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 0 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C8 " "Info: Device EP4CE40F29C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C8 " "Info: Device EP4CE30F29C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C8 " "Info: Device EP4CE55F29C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C8 " "Info: Device EP4CE75F29C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Info: Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 2012 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 2014 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Info: Pin ~ALTERA_DCLK~ is reserved at location P3" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 2016 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Info: Pin ~ALTERA_DATA0~ is reserved at location N7" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 2018 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Info: Pin ~ALTERA_nCEO~ is reserved at location P28" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 2020 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "MDCK2395 " "Info: Entity MDCK2395" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical LJMV0916_0\] " "Info: set_disable_timing \[get_cells -hierarchical LJMV0916_0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_0\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_1\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_1\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_2\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_2\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_3\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_3\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_4\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_4\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_5\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_5\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_6\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_6\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_7\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_7\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical WCRO7487_0\] " "Info: set_disable_timing \[get_cells -hierarchical WCRO7487_0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "pzdyqx_impl " "Info: Entity pzdyqx_impl" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_keepers \{altera_reserved_tdi\}\] -to \[get_keepers \{pzdyqx*\}\] " "Info: set_false_path -from \[get_keepers \{altera_reserved_tdi\}\] -to \[get_keepers \{pzdyqx*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "DE2_115_ADDA.SDC " "Info: Reading SDC File: 'DE2_115_ADDA.SDC'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL Clocks " "Info: Deriving PLL Clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\} " "Info: create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 4 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\} " "Info: create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 4 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call" {  } {  } 0 0 "Clock uncertainty calculation is delayed until the next update_timing_netlist call" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 0 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Info: Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000    CLOCK2_50 " "Info:   20.000    CLOCK2_50" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000    CLOCK3_50 " "Info:   20.000    CLOCK3_50" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "Info:   20.000     CLOCK_50" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " "Info:    8.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  16.000 U1\|pll_100\|altpll_component\|pll\|clk\[1\] " "Info:   16.000 U1\|pll_100\|altpll_component\|pll\|clk\[1\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DE2_115_ADDA_TOP:U1|pll:pll_100|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 467 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk1 (placed in counter C1 of PLL_1) " "Info: Automatically promoted node DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|_clk1 (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 539 3 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DE2_115_ADDA_TOP:U1|pll:pll_100|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 467 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1447 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~CLKDRUSER  " "Info: Automatically promoted node altera_internal_jtag~CLKDRUSER " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1447 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|EPEO2888_7  " "Info: Automatically promoted node pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|EPEO2888_7 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|EPEO2888_7~0 " "Info: Destination node pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|EPEO2888_7~0" {  } { { "pzdyqx.vhd" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/pzdyqx.vhd" 705 -1 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_7~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1681 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "pzdyqx.vhd" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/pzdyqx.vhd" 705 -1 0 } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|EPEO2888_7" } } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1531 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|WCRO7487_0  " "Info: Automatically promoted node pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|WCRO7487_0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "pzdyqx.vhd" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/pzdyqx.vhd" 803 0 0 } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|MDCK2395:\\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1\|WCRO7487_0" } } } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|WCRO7487_0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1553 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~UPDATEUSER  " "Info: Automatically promoted node altera_internal_jtag~UPDATEUSER " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|VELJ8121:JDCF0099\|EHEH8502 " "Info: Destination node pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|VELJ8121:JDCF0099\|EHEH8502" {  } { { "pzdyqx.vhd" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/pzdyqx.vhd" 984 -1 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|EHEH8502 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1468 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 1447 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll clk\[0\] DAC_CLK_A~output " "Warning: PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"DAC_CLK_A~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } } { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 100 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll clk\[0\] DAC_CLK_B~output " "Warning: PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"DAC_CLK_B~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } } { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 101 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll clk\[0\] DAC_WRT_A~output " "Warning: PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"DAC_WRT_A~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } } { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 105 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll clk\[0\] DAC_WRT_B~output " "Warning: PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"DAC_WRT_B~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } } { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 106 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll clk\[1\] ADC_CLK_A~output " "Warning: PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" output port clk\[1\] feeds output pin \"ADC_CLK_A~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } } { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 92 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll clk\[1\] ADC_CLK_B~output " "Warning: PLL \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\" output port clk\[1\] feeds output pin \"ADC_CLK_B~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altpll.tdf" 920 3 0 } } { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } } { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 93 0 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Info: Fitter preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X46_Y37 X57_Y48 " "Info: Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X46_Y37 to location X57_Y48" {  } {  } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 Cyclone IV E " "Warning: 4 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK2_50 3.3-V LVTTL AG14 " "Info: Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { CLOCK2_50 } } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 84 0 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK2_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 104 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK3_50 3.3-V LVTTL AG15 " "Info: Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { CLOCK3_50 } } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 85 0 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK3_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 105 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL A8 " "Info: Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at A8" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 89 0 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 107 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Info: Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 83 0 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 103 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!d! pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Info: Pin I2C_SDAT has a permanently disabled output enable" {  } { { "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1sp1/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/10.1sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 89 0 0 } } { "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "G:/FPGA/DE2_115_ADA/" { { 0 { 0 ""} 0 107 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "411 " "Info: Peak virtual memory: 411 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 17 20:58:31 2011 " "Info: Processing ended: Fri Jun 17 20:58:31 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Info: Elapsed time: 00:00:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:34 " "Info: Total CPU time (on all processors): 00:00:34" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 17 20:58:33 2011 " "Info: Processing started: Fri Jun 17 20:58:33 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 17 20:58:33 2011 " "Info: Processing started: Fri Jun 17 20:58:33 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE2_115_ADDA -c DE2_115_ADDA " "Info: Command: quartus_sta DE2_115_ADDA -c DE2_115_ADDA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #4" {  } {  } 0 0 "qsta_default_script.tcl version: #4" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Info: Core supply voltage is 1.2V" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "MDCK2395 " "Info: Entity MDCK2395" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical LJMV0916_0\] " "Info: set_disable_timing \[get_cells -hierarchical LJMV0916_0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_0\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_1\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_1\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_2\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_2\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_3\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_3\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_4\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_4\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_5\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_5\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_6\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_6\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical EPEO2888_7\] " "Info: set_disable_timing \[get_cells -hierarchical EPEO2888_7\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_disable_timing \[get_cells -hierarchical WCRO7487_0\] " "Info: set_disable_timing \[get_cells -hierarchical WCRO7487_0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "pzdyqx_impl " "Info: Entity pzdyqx_impl" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_keepers \{altera_reserved_tdi\}\] -to \[get_keepers \{pzdyqx*\}\] " "Info: set_false_path -from \[get_keepers \{altera_reserved_tdi\}\] -to \[get_keepers \{pzdyqx*\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "DE2_115_ADDA.SDC " "Info: Reading SDC File: 'DE2_115_ADDA.SDC'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL Clocks " "Info: Deriving PLL Clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\} " "Info: create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 4 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\} " "Info: create_generated_clock -source \{U1\|pll_100\|altpll_component\|pll\|inclk\[0\]\} -divide_by 4 -multiply_by 5 -duty_cycle 50.00 -name \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\} \{U1\|pll_100\|altpll_component\|pll\|clk\[1\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call" {  } {  } 0 0 "Clock uncertainty calculation is delayed until the next update_timing_netlist call" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.550 " "Info: Worst-case setup slack is 3.550" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.550         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     3.550         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   42.288         0.000 altera_reserved_tck  " "Info:    42.288         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.293 " "Info: Worst-case hold slack is 0.293" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.293         0.000 altera_reserved_tck  " "Info:     0.293         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.355         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     0.355         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 43.247 " "Info: Worst-case recovery slack is 43.247" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   43.247         0.000 altera_reserved_tck  " "Info:    43.247         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" {  } {  } 1 0 "Timing requirements not met" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal -2.424 " "Info: Worst-case removal slack is -2.424" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.424        -2.424 altera_reserved_tck  " "Info:    -2.424        -2.424 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.000 " "Info: Worst-case minimum pulse width slack is 3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.000         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     3.000         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.891         0.000 CLOCK_50  " "Info:     9.891         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.000         0.000 CLOCK2_50  " "Info:    16.000         0.000 CLOCK2_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.000         0.000 CLOCK3_50  " "Info:    16.000         0.000 CLOCK3_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   29.350         0.000 altera_reserved_tck  " "Info:    29.350         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.976 " "Info: Worst-case setup slack is 3.976" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.976         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     3.976         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   42.196         0.000 altera_reserved_tck  " "Info:    42.196         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.097 " "Info: Worst-case hold slack is 0.097" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.097         0.000 altera_reserved_tck  " "Info:     0.097         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.338         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     0.338         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 43.624 " "Info: Worst-case recovery slack is 43.624" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   43.624         0.000 altera_reserved_tck  " "Info:    43.624         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" {  } {  } 1 0 "Timing requirements not met" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal -2.375 " "Info: Worst-case removal slack is -2.375" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.375        -2.375 altera_reserved_tck  " "Info:    -2.375        -2.375 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.000 " "Info: Worst-case minimum pulse width slack is 3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.000         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     3.000         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.882         0.000 CLOCK_50  " "Info:     9.882         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.000         0.000 CLOCK2_50  " "Info:    16.000         0.000 CLOCK2_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.000         0.000 CLOCK3_50  " "Info:    16.000         0.000 CLOCK3_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   29.775         0.000 altera_reserved_tck  " "Info:    29.775         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -rise_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -fall_to \[get_clocks \{U1\|pll_100\|altpll_component\|pll\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 6.037 " "Info: Worst-case setup slack is 6.037" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.037         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     6.037         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.805         0.000 altera_reserved_tck  " "Info:    46.805         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.114 " "Info: Worst-case hold slack is 0.114" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.114         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     0.114         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.164         0.000 altera_reserved_tck  " "Info:     0.164         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 46.531 " "Info: Worst-case recovery slack is 46.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.531         0.000 altera_reserved_tck  " "Info:    46.531         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" {  } {  } 1 0 "Timing requirements not met" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal -0.991 " "Info: Worst-case removal slack is -0.991" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.991        -0.991 altera_reserved_tck  " "Info:    -0.991        -0.991 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.753 " "Info: Worst-case minimum pulse width slack is 3.753" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.753         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\]  " "Info:     3.753         0.000 U1\|pll_100\|altpll_component\|pll\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.400         0.000 CLOCK_50  " "Info:     9.400         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.000         0.000 CLOCK2_50  " "Info:    16.000         0.000 CLOCK2_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.000         0.000 CLOCK3_50  " "Info:    16.000         0.000 CLOCK3_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   29.420         0.000 altera_reserved_tck  " "Info:    29.420         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "280 " "Info: Peak virtual memory: 280 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 17 20:58:43 2011 " "Info: Processing ended: Fri Jun 17 20:58:43 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_USED_TIME_LIMITED_CORE" "" "Info: Design contains a time-limited core -- only a single, time-limited programming file can be generated" {  } {  } 0 0 "Design contains a time-limited core -- only a single, time-limited programming file can be generated" 0 0 "" 0 -1}
{ "Warning" "WPGMIO_CAN_NOT_CONVERT_TIME_LIMITED_SOF" "" "Warning: Can't convert time-limited SOF into POF, HEX File, TTF, or RBF" {  } {  } 0 0 "Can't convert time-limited SOF into POF, HEX File, TTF, or RBF" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Info: Peak virtual memory: 430 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 17 20:58:46 2011 " "Info: Processing ended: Fri Jun 17 20:58:46 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Info: Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 71 s " "Info: Quartus II Full Compilation was successful. 0 errors, 71 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
