Quartus II
Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition
15
1298
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --

nco-library|

nco-library|

fir_compiler-library|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
DE2_115_ADDA
# storage
db|DE2_115_ADDA.(0).cnf
db|DE2_115_ADDA.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
de2_115_adda.v
39a75c143d627ed226dc7eb0e953d9d4
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
DE2_115_ADDA_TOP
# storage
db|DE2_115_ADDA.(1).cnf
db|DE2_115_ADDA.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
de2_115_adda_top.v
1db8cd16ff3a3d26bf75bceec93d8a90
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
DE2_115_ADDA_TOP:U1
}
# macro_sequence

# end
# entity
pll
# storage
db|DE2_115_ADDA.(2).cnf
db|DE2_115_ADDA.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pll.v
11bb6ac17298b3b8681ac2d57b8439fb
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
DE2_115_ADDA_TOP:U1|pll:pll_100
}
# macro_sequence
ALTERA_RESERVED_QISALTERA_RESERVED_QIS
# end
# entity
altpll
# storage
db|DE2_115_ADDA.(3).cnf
db|DE2_115_ADDA.(3).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|altpll.tdf
86b75138429c7354c383e2cca01ca9f6
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
LPM_HINT
CBX_MODULE_PREFIX=pll
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
5
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
5
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
4
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
2
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
pllena
-1
3
inclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
configupdate
-1
1
clkswitch
-1
1
scanclkena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# hierarchies {
DE2_115_ADDA_TOP:U1|pll:pll_100|altpll:altpll_component
}
# macro_sequence

# end
# entity
mynco
# storage
db|DE2_115_ADDA.(4).cnf
db|DE2_115_ADDA.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mynco.v
8f37af7953af7851a8d85baf3b92acf3
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1
}
# macro_sequence

# end
# entity
mynco_st
# storage
db|DE2_115_ADDA.(5).cnf
db|DE2_115_ADDA.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mynco_st.v
dea4b5dbd09b83964d5b2f941ceba67
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
13
PARAMETER_SIGNED_DEC
DEF
opr
26
PARAMETER_SIGNED_DEC
DEF
oprp1
27
PARAMETER_SIGNED_DEC
DEF
apr
32
PARAMETER_SIGNED_DEC
DEF
apri
16
PARAMETER_SIGNED_DEC
DEF
aprf
32
PARAMETER_SIGNED_DEC
DEF
aprp
16
PARAMETER_SIGNED_DEC
DEF
aprid
21
PARAMETER_SIGNED_DEC
DEF
dpri
5
PARAMETER_SIGNED_DEC
DEF
rdw
13
PARAMETER_SIGNED_DEC
DEF
rawc
8
PARAMETER_SIGNED_DEC
DEF
rnwc
256
PARAMETER_SIGNED_DEC
DEF
rawf
8
PARAMETER_SIGNED_DEC
DEF
rnwf
256
PARAMETER_SIGNED_DEC
DEF
Pn
16384
PARAMETER_SIGNED_DEC
DEF
mxnbc
3328
PARAMETER_SIGNED_DEC
DEF
mxnbf
3328
PARAMETER_SIGNED_DEC
DEF
rsfc
mynco_sin_c.hex
PARAMETER_STRING
DEF
rsff
mynco_sin_f.hex
PARAMETER_STRING
DEF
rcfc
mynco_cos_c.hex
PARAMETER_STRING
DEF
rcff
mynco_cos_f.hex
PARAMETER_STRING
DEF
nc
1
PARAMETER_SIGNED_DEC
DEF
log2nc
0
PARAMETER_SIGNED_DEC
DEF
outselinit
-1
PARAMETER_SIGNED_DEC
DEF
paci0
0
PARAMETER_SIGNED_DEC
DEF
paci1
0
PARAMETER_SIGNED_DEC
DEF
paci2
0
PARAMETER_SIGNED_DEC
DEF
paci3
0
PARAMETER_SIGNED_DEC
DEF
paci4
0
PARAMETER_SIGNED_DEC
DEF
paci5
0
PARAMETER_SIGNED_DEC
DEF
paci6
0
PARAMETER_SIGNED_DEC
DEF
paci7
0
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst
}
# macro_sequence

# end
# entity
asj_altqmcpipe
# storage
db|DE2_115_ADDA.(6).cnf
db|DE2_115_ADDA.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_altqmcpipe.v
ec26f979da95e41b869aa95ca57731e
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
apr
32
PARAMETER_SIGNED_DEC
USR
lat
1
PARAMETER_SIGNED_DEC
USR
nc
1
PARAMETER_SIGNED_DEC
USR
paci0
0
PARAMETER_SIGNED_DEC
USR
paci1
0
PARAMETER_SIGNED_DEC
USR
paci2
0
PARAMETER_SIGNED_DEC
USR
paci3
0
PARAMETER_SIGNED_DEC
USR
paci4
0
PARAMETER_SIGNED_DEC
USR
paci5
0
PARAMETER_SIGNED_DEC
USR
paci6
0
PARAMETER_SIGNED_DEC
USR
paci7
0
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|DE2_115_ADDA.(7).cnf
db|DE2_115_ADDA.(7).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|lpm_add_sub.tdf
7773cbea1e5cc689e4cbdb2711d832c
7
# user_parameter {
LPM_WIDTH
32
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_v4i
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc
}
# macro_sequence

# end
# entity
add_sub_v4i
# storage
db|DE2_115_ADDA.(8).cnf
db|DE2_115_ADDA.(8).cnf
# case_insensitive
# source_file
db|add_sub_v4i.tdf
68afbca0dc0c48afd95ca32b3dca8f7
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab31
-1
3
datab30
-1
3
datab3
-1
3
datab29
-1
3
datab28
-1
3
datab27
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa31
-1
3
dataa30
-1
3
dataa3
-1
3
dataa29
-1
3
dataa28
-1
3
dataa27
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_v4i:auto_generated
}
# macro_sequence

# end
# entity
asj_dxx_g
# storage
db|DE2_115_ADDA.(9).cnf
db|DE2_115_ADDA.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_dxx_g.v
2ce173e13724313b3c52a778d75cd92
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
dpri
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx_g:ux001
}
# macro_sequence

# end
# entity
asj_dxx
# storage
db|DE2_115_ADDA.(10).cnf
db|DE2_115_ADDA.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_dxx.v
50d0149c40e98362ef52ca6596373945
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
aprid
21
PARAMETER_SIGNED_DEC
USR
dpri
5
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|DE2_115_ADDA.(11).cnf
db|DE2_115_ADDA.(11).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|lpm_add_sub.tdf
7773cbea1e5cc689e4cbdb2711d832c
7
# user_parameter {
LPM_WIDTH
21
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_qth
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002|lpm_add_sub:ux014
}
# macro_sequence

# end
# entity
add_sub_qth
# storage
db|DE2_115_ADDA.(12).cnf
db|DE2_115_ADDA.(12).cnf
# case_insensitive
# source_file
db|add_sub_qth.tdf
acba4619185ffaf6cf5b8931eba062d1
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_qth:auto_generated
}
# macro_sequence

# end
# entity
asj_nco_apr_dxx
# storage
db|DE2_115_ADDA.(13).cnf
db|DE2_115_ADDA.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_apr_dxx.v
2f865a33792c4eb36a965b2a5ae6a3e1
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
apr
32
PARAMETER_SIGNED_DEC
USR
aprid
21
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_apr_dxx:ux0219
}
# macro_sequence

# end
# entity
asj_gam_dp
# storage
db|DE2_115_ADDA.(14).cnf
db|DE2_115_ADDA.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_gam_dp.v
a7f7a7a2c0f6448d2e19b8c3e3a25144
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
apr
16
PARAMETER_SIGNED_DEC
USR
rawc
8
PARAMETER_SIGNED_DEC
USR
rawf
8
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_gam_dp:ux008
}
# macro_sequence

# end
# entity
asj_nco_as_m_dp_cen
# storage
db|DE2_115_ADDA.(15).cnf
db|DE2_115_ADDA.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_as_m_dp_cen.v
d07c12f7e57c1c8b4e96b8c28e3c7a39
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
13
PARAMETER_SIGNED_DEC
USR
raw
8
PARAMETER_SIGNED_DEC
USR
rdw
13
PARAMETER_SIGNED_DEC
USR
rnw
256
PARAMETER_SIGNED_DEC
USR
rf
mynco_sin_c.hex
PARAMETER_STRING
USR
dev
CycloneII
PARAMETER_STRING
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_115_ADDA.(16).cnf
db|DE2_115_ADDA.(16).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
13
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
13
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
256
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
mynco_sin_c.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_4g72
PARAMETER_UNKNOWN
USR
}
# used_port {
q_b
-1
3
q_a
-1
3
clocken0
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_b
-1
1
wren_a
-1
1
data_b
-1
1
data_a
-1
1
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component
}
# macro_sequence

# end
# entity
altsyncram_4g72
# storage
db|DE2_115_ADDA.(17).cnf
db|DE2_115_ADDA.(17).cnf
# case_insensitive
# source_file
db|altsyncram_4g72.tdf
777aa9d71467e1dabc8eaa31c8728c
7
# used_port {
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
mynco_sin_c.hex
cceca6319d59f37eb3c4899618636c94
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4g72:auto_generated
}
# macro_sequence

# end
# entity
asj_nco_as_m_cen
# storage
db|DE2_115_ADDA.(18).cnf
db|DE2_115_ADDA.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_as_m_cen.v
1f1102f237852c4dab39421202b7a32
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
raw
8
PARAMETER_SIGNED_DEC
USR
mpr
13
PARAMETER_SIGNED_DEC
USR
rdw
13
PARAMETER_SIGNED_DEC
USR
rnw
256
PARAMETER_SIGNED_DEC
USR
rf
mynco_sin_f.hex
PARAMETER_STRING
USR
dev
CycloneII
PARAMETER_STRING
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_115_ADDA.(19).cnf
db|DE2_115_ADDA.(19).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
13
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
mynco_sin_f.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_s791
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clocken0
-1
3
clock0
-1
3
address_a
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0
}
# macro_sequence

# end
# entity
altsyncram_s791
# storage
db|DE2_115_ADDA.(20).cnf
db|DE2_115_ADDA.(20).cnf
# case_insensitive
# source_file
db|altsyncram_s791.tdf
aa52d4a8f038ecc9d48fd09efe3ac971
7
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
mynco_sin_f.hex
f338a69061659ae9c3d082abf53e54a3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_s791:auto_generated
}
# macro_sequence

# end
# entity
asj_nco_as_m_cen
# storage
db|DE2_115_ADDA.(21).cnf
db|DE2_115_ADDA.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_as_m_cen.v
1f1102f237852c4dab39421202b7a32
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
raw
8
PARAMETER_SIGNED_DEC
USR
mpr
13
PARAMETER_SIGNED_DEC
USR
rdw
13
PARAMETER_SIGNED_DEC
USR
rnw
256
PARAMETER_SIGNED_DEC
USR
rf
mynco_cos_f.hex
PARAMETER_STRING
USR
dev
CycloneII
PARAMETER_STRING
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DE2_115_ADDA.(22).cnf
db|DE2_115_ADDA.(22).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
13
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
256
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
mynco_cos_f.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_n791
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clocken0
-1
3
clock0
-1
3
address_a
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0
}
# macro_sequence

# end
# entity
altsyncram_n791
# storage
db|DE2_115_ADDA.(23).cnf
db|DE2_115_ADDA.(23).cnf
# case_insensitive
# source_file
db|altsyncram_n791.tdf
e1481aca588dc621b374ab48e07c441b
7
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
mynco_cos_f.hex
6564f2d48a23e85373aa2b68c213045
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_n791:auto_generated
}
# macro_sequence

# end
# entity
mac_i_lpmd
# storage
db|DE2_115_ADDA.(24).cnf
db|DE2_115_ADDA.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|mac_i_lpmd.v
e8184187f92f4892967be4f4819124
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
13
PARAMETER_SIGNED_DEC
USR
opr
26
PARAMETER_SIGNED_DEC
USR
oprp1
27
PARAMETER_SIGNED_DEC
USR
add_p
1
PARAMETER_SIGNED_DEC
DEF
m_p
3
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0
}
# macro_sequence

# end
# entity
lmsd
# storage
db|DE2_115_ADDA.(25).cnf
db|DE2_115_ADDA.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|lmsd.v
1c1aa1abcc218bfed2a142e315b2f77
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
13
PARAMETER_SIGNED_DEC
USR
opr
26
PARAMETER_SIGNED_DEC
USR
sgn
SIGNED
PARAMETER_STRING
USR
pipeline
3
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1
}
# macro_sequence

# end
# entity
lpm_mult
# storage
db|DE2_115_ADDA.(26).cnf
db|DE2_115_ADDA.(26).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|lpm_mult.tdf
dbe17e53a5a2c5dca5b2165e403135ba
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
13
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHB
13
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHP
26
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHR
0
PARAMETER_UNKNOWN
DEF
LPM_WIDTHS
26
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
3
PARAMETER_SIGNED_DEC
USR
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
7
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
LUT
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_7ju
PARAMETER_UNKNOWN
USR
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
USE_AHDL_IMPLEMENTATION
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock
-1
3
clken
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component
}
# macro_sequence

# end
# entity
mult_7ju
# storage
db|DE2_115_ADDA.(27).cnf
db|DE2_115_ADDA.(27).cnf
# case_insensitive
# source_file
db|mult_7ju.tdf
e6add6b995ea77dedabe72144b36e68
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component|mult_7ju:auto_generated
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|lmsd:m_1|lpm_mult:lpm_mult_component|mult_7ju:auto_generated
}
# macro_sequence

# end
# entity
las
# storage
db|DE2_115_ADDA.(28).cnf
db|DE2_115_ADDA.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|las.v
49adc8c7b3ff26961db488c087ff82c0
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
27
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|las:a_0
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|DE2_115_ADDA.(29).cnf
db|DE2_115_ADDA.(29).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|lpm_add_sub.tdf
7773cbea1e5cc689e4cbdb2711d832c
7
# user_parameter {
LPM_WIDTH
27
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_g0j
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock
-1
3
clken
-1
3
add_sub
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|las:a_0|lpm_add_sub:lpm_add_sub_component
}
# macro_sequence

# end
# entity
add_sub_g0j
# storage
db|DE2_115_ADDA.(30).cnf
db|DE2_115_ADDA.(30).cnf
# case_insensitive
# source_file
db|add_sub_g0j.tdf
1ed440dbda7a3388c97c239dac8a832
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
add_sub
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|mac_i_lpmd:m0|las:a_0|lpm_add_sub:lpm_add_sub_component|add_sub_g0j:auto_generated
}
# macro_sequence

# end
# entity
asj_nco_derot
# storage
db|DE2_115_ADDA.(31).cnf
db|DE2_115_ADDA.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_derot.v
f826397138bbe74e5fb11e437675780
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
13
PARAMETER_SIGNED_DEC
USR
rxt
13
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_derot:ux0136
}
# macro_sequence

# end
# entity
asj_nco_mob_w
# storage
db|DE2_115_ADDA.(32).cnf
db|DE2_115_ADDA.(32).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_mob_w.v
a799fd70d8d8a42de8c85d4169b1855d
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
mpr
13
PARAMETER_SIGNED_DEC
USR
opr
26
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_mob_w:blk0
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|DE2_115_ADDA.(33).cnf
db|DE2_115_ADDA.(33).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|lpm_add_sub.tdf
7773cbea1e5cc689e4cbdb2711d832c
7
# user_parameter {
LPM_WIDTH
13
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_i7l
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result
-1
3
dataa
-1
3
clock
-1
3
clken
-1
3
cin
-1
3
aclr
-1
3
datab
-1
1
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component
}
# macro_sequence

# end
# entity
add_sub_i7l
# storage
db|DE2_115_ADDA.(34).cnf
db|DE2_115_ADDA.(34).cnf
# case_insensitive
# source_file
db|add_sub_i7l.tdf
294f3f363e991c9a27ca1b21e5f85f
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
cin
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_i7l:auto_generated
}
# macro_sequence

# end
# entity
asj_nco_isdr
# storage
db|DE2_115_ADDA.(35).cnf
db|DE2_115_ADDA.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
nco-library|asj_nco_isdr.v
67519d1fea29dd78b01ec71951e691fe
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
ctc
12
PARAMETER_SIGNED_DEC
USR
cpr
4
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_isdr:ux710isdr
}
# macro_sequence

# end
# entity
lpm_counter
# storage
db|DE2_115_ADDA.(36).cnf
db|DE2_115_ADDA.(36).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_ori
PARAMETER_UNKNOWN
USR
}
# used_port {
q
-1
3
clock
-1
3
clk_en
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component
}
# macro_sequence

# end
# entity
cntr_ori
# storage
db|DE2_115_ADDA.(37).cnf
db|DE2_115_ADDA.(37).cnf
# case_insensitive
# source_file
db|cntr_ori.tdf
134d43aa3dd271c46412923ab866e8f
7
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|mynco:sin1|mynco_st:mynco_st_inst|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component|cntr_ori:auto_generated
}
# macro_sequence

# end
# entity
filter
# storage
db|DE2_115_ADDA.(38).cnf
db|DE2_115_ADDA.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
filter.v
52c7ef8a8d714ddfdd70a56fc2632db0
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt
}
# macro_sequence

# end
# entity
filter_ast
# storage
db|DE2_115_ADDA.(39).cnf
db|DE2_115_ADDA.(39).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
filter_ast.vhd
1cfed62d9fcabdcd1be85463a60846
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# include_file {
fir_compiler-library|auk_dspip_lib_pkg_fir_101.vhd
6884aaec40fc36f43a411b559556c52
fir_compiler-library|auk_dspip_math_pkg_fir_101.vhd
efc0542ff0a5d772a18063357ad48357
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
auk_dspip_avalon_streaming_sink_fir_101
# storage
db|DE2_115_ADDA.(40).cnf
db|DE2_115_ADDA.(40).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fir_compiler-library|auk_dspip_avalon_streaming_sink_fir_101.vhd
81e34a92b9a4479079b5e830537085
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width_g
13
PARAMETER_SIGNED_DEC
USR
packet_size_g
1
PARAMETER_SIGNED_DEC
USR
fifo_depth_g
7
PARAMETER_SIGNED_DEC
USR
min_data_count_g
2
PARAMETER_SIGNED_DEC
USR
pfc_mode_g
false
PARAMETER_ENUM
USR
sop_eop_calc_g
false
PARAMETER_ENUM
USR
family_g
Cyclone IV E
PARAMETER_STRING
USR
mem_type_g
Auto
PARAMETER_STRING
USR
 constraint(family_g)
1 to 12
PARAMETER_STRING
USR
 constraint(mem_type_g)
1 to 4
PARAMETER_STRING
USR
 constraint(data)
12 downto 0
PARAMETER_STRING
USR
 constraint(packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(at_sink_data)
12 downto 0
PARAMETER_STRING
USR
 constraint(at_sink_error)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
scfifo
# storage
db|DE2_115_ADDA.(41).cnf
db|DE2_115_ADDA.(41).cnf
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|scfifo.tdf
216fefd6725401d49869e8253982231
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
15
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
7
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
3
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
5
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
1
PARAMETER_SIGNED_DEC
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone IV E
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_dhh1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
sclr
-1
1
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo
}
# macro_sequence

# end
# entity
scfifo_dhh1
# storage
db|DE2_115_ADDA.(42).cnf
db|DE2_115_ADDA.(42).cnf
# case_insensitive
# source_file
db|scfifo_dhh1.tdf
1a283f5db556bbdfa50c3225b9d35f2
7
# used_port {
wrreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_6s81
# storage
db|DE2_115_ADDA.(43).cnf
db|DE2_115_ADDA.(43).cnf
# case_insensitive
# source_file
db|a_dpfifo_6s81.tdf
e26cba4e34b35873997c860a8985a
7
# used_port {
wreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo
}
# macro_sequence

# end
# entity
altsyncram_qsf1
# storage
db|DE2_115_ADDA.(44).cnf
db|DE2_115_ADDA.(44).cnf
# case_insensitive
# source_file
db|altsyncram_qsf1.tdf
db431d8276c590ba1896c0f79d2dc4f8
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|altsyncram_qsf1:FIFOram
}
# macro_sequence

# end
# entity
cmpr_gs8
# storage
db|DE2_115_ADDA.(45).cnf
db|DE2_115_ADDA.(45).cnf
# case_insensitive
# source_file
db|cmpr_gs8.tdf
b47c293aadc31657bedf548080e8c5
7
# used_port {
datab2
-1
3
datab1
-1
3
datab0
-1
3
aeb
-1
3
dataa0
-1
1
dataa2
-1
2
dataa1
-1
2
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cmpr_gs8:almost_full_comparer
}
# macro_sequence

# end
# entity
cmpr_gs8
# storage
db|DE2_115_ADDA.(46).cnf
db|DE2_115_ADDA.(46).cnf
# case_insensitive
# source_file
db|cmpr_gs8.tdf
b47c293aadc31657bedf548080e8c5
7
# used_port {
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab2
-1
1
datab0
-1
1
datab1
-1
2
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cmpr_gs8:two_comparison
}
# macro_sequence

# end
# entity
cntr_tnb
# storage
db|DE2_115_ADDA.(47).cnf
db|DE2_115_ADDA.(47).cnf
# case_insensitive
# source_file
db|cntr_tnb.tdf
a6d046e2e1814655d5ee4a2e8568da
7
# used_port {
sclr
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_tnb:rd_ptr_msb
}
# macro_sequence

# end
# entity
cntr_ao7
# storage
db|DE2_115_ADDA.(48).cnf
db|DE2_115_ADDA.(48).cnf
# case_insensitive
# source_file
db|cntr_ao7.tdf
a43c5314113b4035776b26b2774ffb6f
7
# used_port {
updown
-1
3
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_ao7:usedw_counter
}
# macro_sequence

# end
# entity
cntr_unb
# storage
db|DE2_115_ADDA.(49).cnf
db|DE2_115_ADDA.(49).cnf
# case_insensitive
# source_file
db|cntr_unb.tdf
2292e54d22bdd99b80467534513a5f61
7
# used_port {
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_sink_fir_101:sink|scfifo:\normal_fifo:fifo_eab_on:in_fifo|scfifo_dhh1:auto_generated|a_dpfifo_6s81:dpfifo|cntr_unb:wr_ptr
}
# macro_sequence

# end
# entity
auk_dspip_avalon_streaming_source_fir_101
# storage
db|DE2_115_ADDA.(50).cnf
db|DE2_115_ADDA.(50).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fir_compiler-library|auk_dspip_avalon_streaming_source_fir_101.vhd
307b69b7235ad3edf5b930ef7e6fc697
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width_g
13
PARAMETER_SIGNED_DEC
USR
packet_size_g
1
PARAMETER_SIGNED_DEC
USR
have_counter_g
false
PARAMETER_ENUM
USR
counter_limit_g
4
PARAMETER_SIGNED_DEC
USR
multi_channel_g
true
PARAMETER_ENUM
USR
 constraint(data)
12 downto 0
PARAMETER_STRING
USR
 constraint(data_count)
0 downto 0
PARAMETER_STRING
USR
 constraint(packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(at_source_data)
12 downto 0
PARAMETER_STRING
USR
 constraint(at_source_channel)
0 downto 0
PARAMETER_STRING
USR
 constraint(at_source_error)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_source_fir_101:source
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
auk_dspip_avalon_streaming_controller_fir_101
# storage
db|DE2_115_ADDA.(51).cnf
db|DE2_115_ADDA.(51).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fir_compiler-library|auk_dspip_avalon_streaming_controller_fir_101.vhd
d1c563e3c8e84528479abc475f7edfb0
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(sink_packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(source_packet_error)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
filter_st
# storage
db|DE2_115_ADDA.(52).cnf
db|DE2_115_ADDA.(52).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
filter_st.v
3df273526d99030dba321db779fde59
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
DATA_WIDTH
13
PARAMETER_SIGNED_DEC
DEF
COEF_WIDTH
15
PARAMETER_SIGNED_DEC
DEF
ACCUM_WIDTH
34
PARAMETER_SIGNED_DEC
DEF
MSB_RM
0
PARAMETER_SIGNED_DEC
DEF
LSB_RM
21
PARAMETER_SIGNED_DEC
DEF
WIDTH_SAT
13
PARAMETER_SIGNED_DEC
DEF
TOT_WIDTH
34
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore
}
# macro_sequence

# end
# entity
tdl_da_lc
# storage
db|DE2_115_ADDA.(53).cnf
db|DE2_115_ADDA.(53).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|tdl_da_lc.v
d8fe6db6359a79f549d7924808fd532
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
WIDTH
13
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc0n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc1n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc2n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc3n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc4n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc5n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc6n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc7n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc8n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc9n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc10n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc11n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc12n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc13n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc14n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc15n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc16n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc17n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc18n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc19n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc20n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc21n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc22n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc23n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc24n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc25n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc26n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc27n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc28n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc29n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc30n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc31n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc32n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc33n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc34n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc35n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|tdl_da_lc:Utdldalc36n
}
# macro_sequence

# end
# entity
sadd_cen
# storage
db|DE2_115_ADDA.(54).cnf
db|DE2_115_ADDA.(54).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_cen.v
cfa014adb6c74e209fb44a6fc8e7d1c1
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
13
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_0_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_1_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_2_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_3_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_4_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_5_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_6_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_7_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_8_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_9_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_10_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_11_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_12_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_13_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_14_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_15_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_16_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_17_sym_add
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_cen:U_18_sym_add
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(55).cnf
db|DE2_115_ADDA.(55).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
000110011010010110
PARAMETER_UNSIGNED_BIN
USR
C2
000110100100101101
PARAMETER_UNSIGNED_BIN
USR
C3
001100111111000011
PARAMETER_UNSIGNED_BIN
USR
C4
000110101110100110
PARAMETER_UNSIGNED_BIN
USR
C5
001101001000111100
PARAMETER_UNSIGNED_BIN
USR
C6
001101010011010011
PARAMETER_UNSIGNED_BIN
USR
C7
010011101101101001
PARAMETER_UNSIGNED_BIN
USR
C8
000110111000000001
PARAMETER_UNSIGNED_BIN
USR
C9
001101010010010111
PARAMETER_UNSIGNED_BIN
USR
CA
001101011100101110
PARAMETER_UNSIGNED_BIN
USR
CB
010011110111000100
PARAMETER_UNSIGNED_BIN
USR
CC
001101100110100111
PARAMETER_UNSIGNED_BIN
USR
CD
010100000000111101
PARAMETER_UNSIGNED_BIN
USR
CE
010100001011010100
PARAMETER_UNSIGNED_BIN
USR
CF
011010100101101010
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_0_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_1_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_2_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_3_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_4_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_5_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_6_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_7_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_8_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_9_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_10_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_11_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_12_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(56).cnf
db|DE2_115_ADDA.(56).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
111001100101101010
PARAMETER_UNSIGNED_BIN
USR
C2
111001011011010011
PARAMETER_UNSIGNED_BIN
USR
C3
110011000000111101
PARAMETER_UNSIGNED_BIN
USR
C4
111001010001011010
PARAMETER_UNSIGNED_BIN
USR
C5
110010110111000100
PARAMETER_UNSIGNED_BIN
USR
C6
110010101100101101
PARAMETER_UNSIGNED_BIN
USR
C7
101100010010010111
PARAMETER_UNSIGNED_BIN
USR
C8
111001000111111111
PARAMETER_UNSIGNED_BIN
USR
C9
110010101101101001
PARAMETER_UNSIGNED_BIN
USR
CA
110010100011010010
PARAMETER_UNSIGNED_BIN
USR
CB
101100001000111100
PARAMETER_UNSIGNED_BIN
USR
CC
110010011001011001
PARAMETER_UNSIGNED_BIN
USR
CD
101011111111000011
PARAMETER_UNSIGNED_BIN
USR
CE
101011110100101100
PARAMETER_UNSIGNED_BIN
USR
CF
100101011010010110
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur0_n_13_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(57).cnf
db|DE2_115_ADDA.(57).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
000111000000111100
PARAMETER_UNSIGNED_BIN
USR
C2
000111001001010101
PARAMETER_UNSIGNED_BIN
USR
C3
001110001010010001
PARAMETER_UNSIGNED_BIN
USR
C4
000111010001001100
PARAMETER_UNSIGNED_BIN
USR
C5
001110010010001000
PARAMETER_UNSIGNED_BIN
USR
C6
001110011010100001
PARAMETER_UNSIGNED_BIN
USR
C7
010101011011011101
PARAMETER_UNSIGNED_BIN
USR
C8
000111011000011111
PARAMETER_UNSIGNED_BIN
USR
C9
001110011001011011
PARAMETER_UNSIGNED_BIN
USR
CA
001110100001110100
PARAMETER_UNSIGNED_BIN
USR
CB
010101100010110000
PARAMETER_UNSIGNED_BIN
USR
CC
001110101001101011
PARAMETER_UNSIGNED_BIN
USR
CD
010101101010100111
PARAMETER_UNSIGNED_BIN
USR
CE
010101110011000000
PARAMETER_UNSIGNED_BIN
USR
CF
011100110011111100
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_0_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_1_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_2_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_3_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_4_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_5_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_6_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_7_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_8_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_9_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_10_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_11_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_12_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(58).cnf
db|DE2_115_ADDA.(58).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
111000111111000100
PARAMETER_UNSIGNED_BIN
USR
C2
111000110110101011
PARAMETER_UNSIGNED_BIN
USR
C3
110001110101101111
PARAMETER_UNSIGNED_BIN
USR
C4
111000101110110100
PARAMETER_UNSIGNED_BIN
USR
C5
110001101101111000
PARAMETER_UNSIGNED_BIN
USR
C6
110001100101011111
PARAMETER_UNSIGNED_BIN
USR
C7
101010100100100011
PARAMETER_UNSIGNED_BIN
USR
C8
111000100111100001
PARAMETER_UNSIGNED_BIN
USR
C9
110001100110100101
PARAMETER_UNSIGNED_BIN
USR
CA
110001011110001100
PARAMETER_UNSIGNED_BIN
USR
CB
101010011101010000
PARAMETER_UNSIGNED_BIN
USR
CC
110001010110010101
PARAMETER_UNSIGNED_BIN
USR
CD
101010010101011001
PARAMETER_UNSIGNED_BIN
USR
CE
101010001101000000
PARAMETER_UNSIGNED_BIN
USR
CF
100011001100000100
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur1_n_13_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(59).cnf
db|DE2_115_ADDA.(59).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
000111011111001101
PARAMETER_UNSIGNED_BIN
USR
C2
000111100101010101
PARAMETER_UNSIGNED_BIN
USR
C3
001111000100100010
PARAMETER_UNSIGNED_BIN
USR
C4
000111101010110110
PARAMETER_UNSIGNED_BIN
USR
C5
001111001010000011
PARAMETER_UNSIGNED_BIN
USR
C6
001111010000001011
PARAMETER_UNSIGNED_BIN
USR
C7
010110101111011000
PARAMETER_UNSIGNED_BIN
USR
C8
000111101111110000
PARAMETER_UNSIGNED_BIN
USR
C9
001111001110111101
PARAMETER_UNSIGNED_BIN
USR
CA
001111010101000101
PARAMETER_UNSIGNED_BIN
USR
CB
010110110100010010
PARAMETER_UNSIGNED_BIN
USR
CC
001111011010100110
PARAMETER_UNSIGNED_BIN
USR
CD
010110111001110011
PARAMETER_UNSIGNED_BIN
USR
CE
010110111111111011
PARAMETER_UNSIGNED_BIN
USR
CF
011110011111001000
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_0_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_1_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_2_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_3_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_4_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_5_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_6_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_7_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_8_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_9_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_10_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_11_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_12_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(60).cnf
db|DE2_115_ADDA.(60).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
111000100000110011
PARAMETER_UNSIGNED_BIN
USR
C2
111000011010101011
PARAMETER_UNSIGNED_BIN
USR
C3
110000111011011110
PARAMETER_UNSIGNED_BIN
USR
C4
111000010101001010
PARAMETER_UNSIGNED_BIN
USR
C5
110000110101111101
PARAMETER_UNSIGNED_BIN
USR
C6
110000101111110101
PARAMETER_UNSIGNED_BIN
USR
C7
101001010000101000
PARAMETER_UNSIGNED_BIN
USR
C8
111000010000010000
PARAMETER_UNSIGNED_BIN
USR
C9
110000110001000011
PARAMETER_UNSIGNED_BIN
USR
CA
110000101010111011
PARAMETER_UNSIGNED_BIN
USR
CB
101001001011101110
PARAMETER_UNSIGNED_BIN
USR
CC
110000100101011010
PARAMETER_UNSIGNED_BIN
USR
CD
101001000110001101
PARAMETER_UNSIGNED_BIN
USR
CE
101001000000000101
PARAMETER_UNSIGNED_BIN
USR
CF
100001100000111000
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur2_n_13_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(61).cnf
db|DE2_115_ADDA.(61).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
000111110100000010
PARAMETER_UNSIGNED_BIN
USR
C2
000111110111101010
PARAMETER_UNSIGNED_BIN
USR
C3
001111101011101100
PARAMETER_UNSIGNED_BIN
USR
C4
000111111010101001
PARAMETER_UNSIGNED_BIN
USR
C5
001111101110101011
PARAMETER_UNSIGNED_BIN
USR
C6
001111110010010011
PARAMETER_UNSIGNED_BIN
USR
C7
010111100110010101
PARAMETER_UNSIGNED_BIN
USR
C8
000111111100111110
PARAMETER_UNSIGNED_BIN
USR
C9
001111110001000000
PARAMETER_UNSIGNED_BIN
USR
CA
001111110100101000
PARAMETER_UNSIGNED_BIN
USR
CB
010111101000101010
PARAMETER_UNSIGNED_BIN
USR
CC
001111110111100111
PARAMETER_UNSIGNED_BIN
USR
CD
010111101011101001
PARAMETER_UNSIGNED_BIN
USR
CE
010111101111010001
PARAMETER_UNSIGNED_BIN
USR
CF
011111100011010011
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_0_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_1_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_2_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_3_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_4_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_5_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_6_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_7_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_8_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_9_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_10_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_11_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_12_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(62).cnf
db|DE2_115_ADDA.(62).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
111000001011111110
PARAMETER_UNSIGNED_BIN
USR
C2
111000001000010110
PARAMETER_UNSIGNED_BIN
USR
C3
110000010100010100
PARAMETER_UNSIGNED_BIN
USR
C4
111000000101010111
PARAMETER_UNSIGNED_BIN
USR
C5
110000010001010101
PARAMETER_UNSIGNED_BIN
USR
C6
110000001101101101
PARAMETER_UNSIGNED_BIN
USR
C7
101000011001101011
PARAMETER_UNSIGNED_BIN
USR
C8
111000000011000010
PARAMETER_UNSIGNED_BIN
USR
C9
110000001111000000
PARAMETER_UNSIGNED_BIN
USR
CA
110000001011011000
PARAMETER_UNSIGNED_BIN
USR
CB
101000010111010110
PARAMETER_UNSIGNED_BIN
USR
CC
110000001000011001
PARAMETER_UNSIGNED_BIN
USR
CD
101000010100010111
PARAMETER_UNSIGNED_BIN
USR
CE
101000010000101111
PARAMETER_UNSIGNED_BIN
USR
CF
100000011100101101
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur3_n_13_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(63).cnf
db|DE2_115_ADDA.(63).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
000111111110101001
PARAMETER_UNSIGNED_BIN
USR
C2
000111111111101001
PARAMETER_UNSIGNED_BIN
USR
C3
001111111110010010
PARAMETER_UNSIGNED_BIN
USR
C4
000111111111111111
PARAMETER_UNSIGNED_BIN
USR
C5
001111111110101000
PARAMETER_UNSIGNED_BIN
USR
C6
001111111111101000
PARAMETER_UNSIGNED_BIN
USR
C7
010111111110010001
PARAMETER_UNSIGNED_BIN
USR
C8
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C9
000111111110101001
PARAMETER_UNSIGNED_BIN
USR
CA
000111111111101001
PARAMETER_UNSIGNED_BIN
USR
CB
001111111110010010
PARAMETER_UNSIGNED_BIN
USR
CC
000111111111111111
PARAMETER_UNSIGNED_BIN
USR
CD
001111111110101000
PARAMETER_UNSIGNED_BIN
USR
CE
001111111111101000
PARAMETER_UNSIGNED_BIN
USR
CF
010111111110010001
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_0_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_1_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_2_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_3_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_4_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_5_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_6_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_7_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_8_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_9_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_10_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_11_pp
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_12_pp
}
# macro_sequence

# end
# entity
rom_lut_r_cen
# storage
db|DE2_115_ADDA.(64).cnf
db|DE2_115_ADDA.(64).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|rom_lut_r_cen.v
33507dcd1a8454475da59bbc321fd
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
C0
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C1
111000000001010111
PARAMETER_UNSIGNED_BIN
USR
C2
111000000000010111
PARAMETER_UNSIGNED_BIN
USR
C3
110000000001101110
PARAMETER_UNSIGNED_BIN
USR
C4
111000000000000001
PARAMETER_UNSIGNED_BIN
USR
C5
110000000001011000
PARAMETER_UNSIGNED_BIN
USR
C6
110000000000011000
PARAMETER_UNSIGNED_BIN
USR
C7
101000000001101111
PARAMETER_UNSIGNED_BIN
USR
C8
000000000000000000
PARAMETER_UNSIGNED_BIN
USR
C9
111000000001010111
PARAMETER_UNSIGNED_BIN
USR
CA
111000000000010111
PARAMETER_UNSIGNED_BIN
USR
CB
110000000001101110
PARAMETER_UNSIGNED_BIN
USR
CC
111000000000000001
PARAMETER_UNSIGNED_BIN
USR
CD
110000000001011000
PARAMETER_UNSIGNED_BIN
USR
CE
110000000000011000
PARAMETER_UNSIGNED_BIN
USR
CF
101000000001101111
PARAMETER_UNSIGNED_BIN
USR
DATA_WIDTH
18
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|rom_lut_r_cen:Ur4_n_13_pp
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(65).cnf
db|DE2_115_ADDA.(65).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
31
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_5_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_0_n_6_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_4_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_5_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_0_n_6_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_4_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_5_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_0_n_6_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_4_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_5_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_0_n_6_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_4_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_5_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_0_n_6_n
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(66).cnf
db|DE2_115_ADDA.(66).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
32
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_1_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_1_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_1_n_3_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_2_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_1_n_3_n
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(67).cnf
db|DE2_115_ADDA.(67).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
33
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_2_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_2_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_2_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_2_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_2_n_1_n
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(68).cnf
db|DE2_115_ADDA.(68).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
34
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_1_lut_l_3_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_3_lut_l_3_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(69).cnf
db|DE2_115_ADDA.(69).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
35
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_1_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_0_n_2_n
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(70).cnf
db|DE2_115_ADDA.(70).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
36
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_0_n
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_1_n_1_n
}
# macro_sequence

# end
# entity
sadd_lpm_cen
# storage
db|DE2_115_ADDA.(71).cnf
db|DE2_115_ADDA.(71).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|sadd_lpm_cen.v
e41ec75e73dc63336fd6d34f848f63
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IN_WIDTH
37
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|sadd_lpm_cen:Uadd_cen_l_2_n_0_n
}
# macro_sequence

# end
# entity
mac_tl
# storage
db|DE2_115_ADDA.(72).cnf
db|DE2_115_ADDA.(72).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|mac_tl.v
5d8a7139b18c384141bc9744b6558c
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
DATA_WIDTH
38
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|mac_tl:Umtl
}
# macro_sequence

# end
# entity
par_ctrl
# storage
db|DE2_115_ADDA.(73).cnf
db|DE2_115_ADDA.(73).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_compiler-library|par_ctrl.v
f6c3277931251ced51bce9e6bded9a1
8
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
REG_LEN
10
PARAMETER_SIGNED_DEC
USR
REG_BIT
4
PARAMETER_SIGNED_DEC
USR
CH_WIDTH
0
PARAMETER_SIGNED_DEC
USR
NUM_CH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
DE2_115_ADDA_TOP:U1|filter:filt|filter_ast:filter_ast_inst|filter_st:fircore|par_ctrl:Uctrl
}
# macro_sequence

# end
# entity
pzdyqx
# storage
db|DE2_115_ADDA.(74).cnf
db|DE2_115_ADDA.(74).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
pzdyqx0
10
PARAMETER_UNKNOWN
USR
pzdyqx9
1
PARAMETER_SIGNED_DEC
DEF
SLD_NODE_INFO
552448
PARAMETER_SIGNED_DEC
DEF
pzdyqx5
2
PARAMETER_UNKNOWN
USR
pzdyqx6
0110101011110111000000000001010001101010111101110000000000010010
PARAMETER_UNKNOWN
USR
pzdyqx1
3600
PARAMETER_UNKNOWN
USR
pzdyqx3
12
PARAMETER_UNKNOWN
USR
pzdyqx2
0
PARAMETER_UNKNOWN
USR
pzdyqx4
1
PARAMETER_UNKNOWN
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
pzdyqx_impl
# storage
db|DE2_115_ADDA.(75).cnf
db|DE2_115_ADDA.(75).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
pzdyqx0
10
PARAMETER_SIGNED_DEC
USR
pzdyqx9
1
PARAMETER_SIGNED_DEC
USR
pzdyqx5
2
PARAMETER_SIGNED_DEC
USR
pzdyqx6
0110101011110111000000000001010001101010111101110000000000010010
PARAMETER_UNSIGNED_BIN
USR
pzdyqx1
3600
PARAMETER_SIGNED_DEC
USR
pzdyqx3
12
PARAMETER_SIGNED_DEC
USR
pzdyqx2
0
PARAMETER_SIGNED_DEC
USR
pzdyqx4
1
PARAMETER_SIGNED_DEC
USR
 constraint(pzdyqx6)
0 to 63
PARAMETER_STRING
USR
 constraint(ir_in)
1 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
1 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
MDCK2395
# storage
db|DE2_115_ADDA.(76).cnf
db|DE2_115_ADDA.(76).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
osc_stages
14
PARAMETER_SIGNED_DEC
USR
osc_prescaler
8
PARAMETER_SIGNED_DEC
USR
clk_gen_width
27
PARAMETER_SIGNED_DEC
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
CJQJ5354
# storage
db|DE2_115_ADDA.(77).cnf
db|DE2_115_ADDA.(77).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width
19
PARAMETER_SIGNED_DEC
USR
modulus
0
PARAMETER_SIGNED_DEC
USR
 constraint(kvqq4224)
18 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
CJQJ5354
# storage
db|DE2_115_ADDA.(78).cnf
db|DE2_115_ADDA.(78).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width
12
PARAMETER_SIGNED_DEC
USR
modulus
3600
PARAMETER_SIGNED_DEC
USR
 constraint(kvqq4224)
11 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
PZMU7345
# storage
db|DE2_115_ADDA.(79).cnf
db|DE2_115_ADDA.(79).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
width
13
PARAMETER_SIGNED_DEC
USR
 constraint(yjoq9945)
12 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
VELJ8121
# storage
db|DE2_115_ADDA.(80).cnf
db|DE2_115_ADDA.(80).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|pzdyqx.vhd
719912c539beca52296673aba6df5442
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
n_bits
104
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(gisa9786)
103 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_hub
# storage
db|DE2_115_ADDA.(81).cnf
db|DE2_115_ADDA.(81).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
4
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone IV E
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
4
PARAMETER_UNKNOWN
USR
node_info
00000000000010000110111000000000
PARAMETER_UNSIGNED_BIN
USR
compilation_mode
1
PARAMETER_UNKNOWN
USR
BROADCAST_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
FORCE_IR_CAPTURE_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_shadow_jsm
# storage
db|DE2_115_ADDA.(82).cnf
db|DE2_115_ADDA.(82).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
1
PARAMETER_SIGNED_DEC
USR
ip_minor_version
4
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|DE2_115_ADDA.(83).cnf
db|DE2_115_ADDA.(83).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1sp1|quartus|libraries|megafunctions|sld_rom_sr.vhd
c8a299171b404a8be9d59988f836b14
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
64
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
63 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1sp1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# complete

