{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 17 21:12:16 2011 " "Info: Processing started: Fri Jun 17 21:12:16 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_115_ADDA -c DE2_115_ADDA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco91_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco91_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco91_st " "Info: Found entity 1: nco91_st" {  } { { "nco91_st.v" "" { Text "G:/FPGA/DE2_115_ADA/nco91_st.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco91.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco91.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco91 " "Info: Found entity 1: nco91" {  } { { "nco91.v" "" { Text "G:/FPGA/DE2_115_ADA/nco91.v" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_add.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lpm_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add " "Info: Found entity 1: lpm_add" {  } { { "lpm_add.v" "" { Text "G:/FPGA/DE2_115_ADA/lpm_add.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de2_115_adda_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file de2_115_adda_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_115_ADDA_TOP " "Info: Found entity 1: DE2_115_ADDA_TOP" {  } { { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mynco_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mynco_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 mynco_st " "Info: Found entity 1: mynco_st" {  } { { "mynco_st.v" "" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mynco.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mynco.v" { { "Info" "ISGN_ENTITY_NAME" "1 mynco " "Info: Found entity 1: mynco" {  } { { "mynco.v" "" { Text "G:/FPGA/DE2_115_ADA/mynco.v" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WCPT_PRELIMINARY_FAMILY_SUPPORT" "FIR_Compiler (6AF7_0012) Cyclone IV E " "Warning: Support for IP core FIR_Compiler (6AF7_0012) in device family Cyclone IV E is preliminary and specifications are subject to change" {  } {  } 0 0 "Support for IP core %1!s! in device family %2!s! is preliminary and specifications are subject to change" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/auk_dspip_lib_pkg_fir_101.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file fir_compiler-library/auk_dspip_lib_pkg_fir_101.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg_fir_101 " "Info: Found design unit 1: auk_dspip_lib_pkg_fir_101" {  } { { "fir_compiler-library/auk_dspip_lib_pkg_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_lib_pkg_fir_101.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/auk_dspip_math_pkg_fir_101.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file fir_compiler-library/auk_dspip_math_pkg_fir_101.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg_fir_101 " "Info: Found design unit 1: auk_dspip_math_pkg_fir_101" {  } { { "fir_compiler-library/auk_dspip_math_pkg_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_math_pkg_fir_101.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg_fir_101-body " "Info: Found design unit 2: auk_dspip_math_pkg_fir_101-body" {  } { { "fir_compiler-library/auk_dspip_math_pkg_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_math_pkg_fir_101.vhd" 115 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "filter_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file filter_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 filter_st " "Info: Found entity 1: filter_st" {  } { { "filter_st.v" "" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "filter_ast.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file filter_ast.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 filter_ast-struct " "Info: Found design unit 1: filter_ast-struct" {  } { { "filter_ast.vhd" "" { Text "G:/FPGA/DE2_115_ADA/filter_ast.vhd" 59 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 filter_ast " "Info: Found entity 1: filter_ast" {  } { { "filter_ast.vhd" "" { Text "G:/FPGA/DE2_115_ADA/filter_ast.vhd" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "filter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 filter " "Info: Found entity 1: filter" {  } { { "filter.v" "" { Text "G:/FPGA/DE2_115_ADA/filter.v" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ovalid DE2_115_ADDA_TOP.v(101) " "Warning (10236): Verilog HDL Implicit Net warning at DE2_115_ADDA_TOP.v(101): created implicit net for \"ovalid\"" {  } { { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 101 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "de2_115_adda.v 1 1 " "Warning: Using design file de2_115_adda.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_115_ADDA " "Info: Found entity 1: DE2_115_ADDA" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_115_ADDA " "Info: Elaborating entity \"DE2_115_ADDA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "I2C_SCLK de2_115_adda.v(88) " "Warning (10034): Output port \"I2C_SCLK\" at de2_115_adda.v(88) has no driver" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 88 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DE2_115_ADDA_TOP DE2_115_ADDA_TOP:U1 " "Info: Elaborating entity \"DE2_115_ADDA_TOP\" for hierarchy \"DE2_115_ADDA_TOP:U1\"" {  } { { "de2_115_adda.v" "U1" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 130 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phasinc2 DE2_115_ADDA_TOP.v(72) " "Warning (10036): Verilog HDL or VHDL warning at DE2_115_ADDA_TOP.v(72): object \"phasinc2\" assigned a value but never read" {  } { { "DE2_115_ADDA_TOP.v" "" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 72 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll DE2_115_ADDA_TOP:U1\|pll:pll_100 " "Info: Elaborating entity \"pll\" for hierarchy \"DE2_115_ADDA_TOP:U1\|pll:pll_100\"" {  } { { "DE2_115_ADDA_TOP.v" "pll_100" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 93 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\"" {  } { { "pll.v" "altpll_component" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\"" {  } { { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Info: Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Info: Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 4 " "Info: Parameter \"clk1_divide_by\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Info: Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Info: Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Info: Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Info: Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Info: Parameter \"intended_device_family\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Info: Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Info: Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Info: Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Info: Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Info: Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_USED " "Info: Parameter \"port_pllena\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Info: Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Info: Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Info: Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Info: Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Info: Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Info: Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "pll.v" "" { Text "G:/FPGA/DE2_115_ADA/pll.v" 106 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mynco DE2_115_ADDA_TOP:U1\|mynco:sin1 " "Info: Elaborating entity \"mynco\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\"" {  } { { "DE2_115_ADDA_TOP.v" "sin1" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 102 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mynco_st DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst " "Info: Elaborating entity \"mynco_st\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\"" {  } { { "mynco.v" "mynco_st_inst" { Text "G:/FPGA/DE2_115_ADA/mynco.v" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "select_s mynco_st.v(88) " "Warning (10036): Verilog HDL or VHDL warning at mynco_st.v(88): object \"select_s\" assigned a value but never read" {  } { { "mynco_st.v" "" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 88 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WCPT_PRELIMINARY_FAMILY_SUPPORT" "\"NCO\" (6AF7_0014) Cyclone IV E " "Warning: Support for IP core \"NCO\" (6AF7_0014) in device family Cyclone IV E is preliminary and specifications are subject to change" {  } {  } 0 0 "Support for IP core %1!s! in device family %2!s! is preliminary and specifications are subject to change" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_altqmcpipe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_altqmcpipe.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_altqmcpipe " "Info: Found entity 1: asj_altqmcpipe" {  } { { "asj_altqmcpipe.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_altqmcpipe.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_altqmcpipe DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000 " "Info: Elaborating entity \"asj_altqmcpipe\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\"" {  } { { "mynco_st.v" "ux000" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 104 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" {  } { { "asj_altqmcpipe.v" "acc" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_altqmcpipe.v" 52 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_v4i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_v4i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_v4i " "Info: Found entity 1: add_sub_v4i" {  } { { "db/add_sub_v4i.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_v4i.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_v4i DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated " "Info: Elaborating entity \"add_sub_v4i\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_v4i:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_dxx_g.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_dxx_g.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_dxx_g " "Info: Found entity 1: asj_dxx_g" {  } { { "asj_dxx_g.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx_g.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_dxx_g DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001 " "Info: Elaborating entity \"asj_dxx_g\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx_g:ux001\"" {  } { { "mynco_st.v" "ux001" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 122 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_dxx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_dxx.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_dxx " "Info: Found entity 1: asj_dxx" {  } { { "asj_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_dxx DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002 " "Info: Elaborating entity \"asj_dxx\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\"" {  } { { "mynco_st.v" "ux002" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 131 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\"" {  } { { "asj_dxx.v" "ux014" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\"" {  } { { "asj_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 41 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 21 " "Info: Parameter \"lpm_width\" = \"21\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_dxx.v" 41 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qth.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qth.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qth " "Info: Found entity 1: add_sub_qth" {  } { { "db/add_sub_qth.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_qth.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_qth DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated " "Info: Elaborating entity \"add_sub_qth\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_qth:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_apr_dxx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_apr_dxx.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_apr_dxx " "Info: Found entity 1: asj_nco_apr_dxx" {  } { { "asj_nco_apr_dxx.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_apr_dxx.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_apr_dxx DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_apr_dxx:ux0219 " "Info: Elaborating entity \"asj_nco_apr_dxx\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_apr_dxx:ux0219\"" {  } { { "mynco_st.v" "ux0219" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 138 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_gam_dp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_gam_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_gam_dp " "Info: Found entity 1: asj_gam_dp" {  } { { "asj_gam_dp.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_gam_dp.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_gam_dp DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_gam_dp:ux008 " "Info: Elaborating entity \"asj_gam_dp\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_gam_dp:ux008\"" {  } { { "mynco_st.v" "ux008" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 150 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_as_m_dp_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_as_m_dp_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_dp_cen " "Info: Found entity 1: asj_nco_as_m_dp_cen" {  } { { "asj_nco_as_m_dp_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_dp_cen DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220 " "Info: Elaborating entity \"asj_nco_as_m_dp_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\"" {  } { { "mynco_st.v" "ux0220" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 162 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" {  } { { "asj_nco_as_m_dp_cen.v" "altsyncram_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 83 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" {  } { { "asj_nco_as_m_dp_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 83 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Info: Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 13 " "Info: Parameter \"width_a\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 13 " "Info: Parameter \"width_b\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Info: Parameter \"widthad_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Info: Parameter \"numwords_b\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Info: Parameter \"width_byteena_b\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Info: Parameter \"outdata_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Info: Parameter \"indata_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Info: Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Info: Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Info: Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Info: Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file mynco_sin_c.hex " "Info: Parameter \"init_file\" = \"mynco_sin_c.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CycloneII " "Info: Parameter \"intended_device_family\" = \"CycloneII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_as_m_dp_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_dp_cen.v" 83 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4g72.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4g72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4g72 " "Info: Found entity 1: altsyncram_4g72" {  } { { "db/altsyncram_4g72.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_4g72.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4g72 DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated " "Info: Elaborating entity \"altsyncram_4g72\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4g72:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_as_m_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_as_m_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_cen " "Info: Found entity 1: asj_nco_as_m_cen" {  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122 " "Info: Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\"" {  } { { "mynco_st.v" "ux0122" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 174 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "altsyncram_component0" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 13 " "Info: Parameter \"width_a\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file mynco_sin_f.hex " "Info: Parameter \"init_file\" = \"mynco_sin_f.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CycloneII " "Info: Parameter \"intended_device_family\" = \"CycloneII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s791.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s791.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s791 " "Info: Found entity 1: altsyncram_s791" {  } { { "db/altsyncram_s791.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_s791.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s791 DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_s791:auto_generated " "Info: Elaborating entity \"altsyncram_s791\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_s791:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123 " "Info: Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\"" {  } { { "mynco_st.v" "ux0123" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 186 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "altsyncram_component0" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" {  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 13 " "Info: Parameter \"width_a\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Info: Parameter \"widthad_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Info: Parameter \"numwords_a\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Info: Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Info: Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file mynco_cos_f.hex " "Info: Parameter \"init_file\" = \"mynco_cos_f.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CycloneII " "Info: Parameter \"intended_device_family\" = \"CycloneII\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_as_m_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_as_m_cen.v" 39 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_n791.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n791.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_n791 " "Info: Found entity 1: altsyncram_n791" {  } { { "db/altsyncram_n791.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_n791.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_n791 DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_n791:auto_generated " "Info: Elaborating entity \"altsyncram_n791\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_n791:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 790 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/mac_i_lpmd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/mac_i_lpmd.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_i_lpmd " "Info: Found entity 1: mac_i_lpmd" {  } { { "mac_i_lpmd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/mac_i_lpmd.v" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_i_lpmd DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0 " "Info: Elaborating entity \"mac_i_lpmd\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\"" {  } { { "mynco_st.v" "m0" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 202 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/lmsd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/lmsd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lmsd " "Info: Found entity 1: lmsd" {  } { { "lmsd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 50 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lmsd DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0 " "Info: Elaborating entity \"lmsd\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\"" {  } { { "mac_i_lpmd.v" "m_0" { Text "G:/FPGA/DE2_115_ADA/nco-library/mac_i_lpmd.v" 59 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\"" {  } { { "lmsd.v" "lpm_mult_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\"" {  } { { "lmsd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 13 " "Info: Parameter \"lpm_widtha\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 13 " "Info: Parameter \"lpm_widthb\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 26 " "Info: Parameter \"lpm_widthp\" = \"26\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 26 " "Info: Parameter \"lpm_widths\" = \"26\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Info: Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=7 " "Info: Parameter \"lpm_hint\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 3 " "Info: Parameter \"lpm_pipeline\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "lmsd.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/lmsd.v" 75 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_7ju.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_7ju.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_7ju " "Info: Found entity 1: mult_7ju" {  } { { "db/mult_7ju.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/mult_7ju.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_7ju DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\|mult_7ju:auto_generated " "Info: Elaborating entity \"mult_7ju\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|lmsd:m_0\|lpm_mult:lpm_mult_component\|mult_7ju:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/las.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/las.v" { { "Info" "ISGN_ENTITY_NAME" "1 las " "Info: Found entity 1: las" {  } { { "las.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "las DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0 " "Info: Elaborating entity \"las\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\"" {  } { { "mac_i_lpmd.v" "a_0" { Text "G:/FPGA/DE2_115_ADA/nco-library/mac_i_lpmd.v" 82 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "las.v" "lpm_add_sub_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 61 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "las.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 61 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 27 " "Info: Parameter \"lpm_width\" = \"27\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UNUSED " "Info: Parameter \"lpm_direction\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "las.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/las.v" 61 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_g0j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_g0j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_g0j " "Info: Found entity 1: add_sub_g0j" {  } { { "db/add_sub_g0j.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_g0j.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_g0j DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\|add_sub_g0j:auto_generated " "Info: Elaborating entity \"add_sub_g0j\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|mac_i_lpmd:m0\|las:a_0\|lpm_add_sub:lpm_add_sub_component\|add_sub_g0j:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_derot.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_derot.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_derot " "Info: Found entity 1: asj_nco_derot" {  } { { "asj_nco_derot.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_derot.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_derot DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_derot:ux0136 " "Info: Elaborating entity \"asj_nco_derot\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_derot:ux0136\"" {  } { { "mynco_st.v" "ux0136" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 215 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_mob_w.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_mob_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mob_w " "Info: Found entity 1: asj_nco_mob_w" {  } { { "asj_nco_mob_w.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_w DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0 " "Info: Elaborating entity \"asj_nco_mob_w\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\"" {  } { { "mynco_st.v" "blk0" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 225 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "asj_nco_mob_w.v" "lpm_add_sub_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "asj_nco_mob_w.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 54 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 13 " "Info: Parameter \"lpm_width\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_mob_w.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_mob_w.v" 54 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_i7l.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_i7l.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_i7l " "Info: Found entity 1: add_sub_i7l" {  } { { "db/add_sub_i7l.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/add_sub_i7l.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_i7l DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_i7l:auto_generated " "Info: Elaborating entity \"add_sub_i7l\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_i7l:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nco-library/asj_nco_isdr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nco-library/asj_nco_isdr.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Info: Found entity 1: asj_nco_isdr" {  } { { "asj_nco_isdr.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr " "Info: Elaborating entity \"asj_nco_isdr\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\"" {  } { { "mynco_st.v" "ux710isdr" { Text "G:/FPGA/DE2_115_ADA/mynco_st.v" 236 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" {  } { { "asj_nco_isdr.v" "lpm_counter_component" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 33 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" {  } { { "asj_nco_isdr.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 33 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Instantiated megafunction \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 4 " "Info: Parameter \"lpm_width\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Info: Parameter \"lpm_type\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Info: Parameter \"lpm_direction\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "asj_nco_isdr.v" "" { Text "G:/FPGA/DE2_115_ADA/nco-library/asj_nco_isdr.v" 33 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ori.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ori.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ori " "Info: Found entity 1: cntr_ori" {  } { { "db/cntr_ori.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cntr_ori.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ori DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated " "Info: Elaborating entity \"cntr_ori\" for hierarchy \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "filter DE2_115_ADDA_TOP:U1\|filter:filt " "Info: Elaborating entity \"filter\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\"" {  } { { "DE2_115_ADDA_TOP.v" "filt" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 115 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "filter_ast DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst " "Info: Elaborating entity \"filter_ast\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\"" {  } { { "filter.v" "filter_ast_inst" { Text "G:/FPGA/DE2_115_ADA/filter.v" 68 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_101.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_101.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink_fir_101-rtl " "Info: Found design unit 1: auk_dspip_avalon_streaming_sink_fir_101-rtl" {  } { { "auk_dspip_avalon_streaming_sink_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_101.vhd" 93 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink_fir_101 " "Info: Found entity 1: auk_dspip_avalon_streaming_sink_fir_101" {  } { { "auk_dspip_avalon_streaming_sink_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_101.vhd" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink_fir_101 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink " "Info: Elaborating entity \"auk_dspip_avalon_streaming_sink_fir_101\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\"" {  } { { "filter_ast.vhd" "sink" { Text "G:/FPGA/DE2_115_ADA/filter_ast.vhd" 91 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo " "Info: Elaborating entity \"scfifo\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\"" {  } { { "auk_dspip_avalon_streaming_sink_fir_101.vhd" "\\normal_fifo:fifo_eab_on:in_fifo" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_101.vhd" 648 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_dhh1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_dhh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_dhh1 " "Info: Found entity 1: scfifo_dhh1" {  } { { "db/scfifo_dhh1.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/scfifo_dhh1.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_dhh1 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated " "Info: Elaborating entity \"scfifo_dhh1\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/10.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_6s81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_6s81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_6s81 " "Info: Found entity 1: a_dpfifo_6s81" {  } { { "db/a_dpfifo_6s81.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_6s81 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo " "Info: Elaborating entity \"a_dpfifo_6s81\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\"" {  } { { "db/scfifo_dhh1.tdf" "dpfifo" { Text "G:/FPGA/DE2_115_ADA/db/scfifo_dhh1.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qsf1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qsf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qsf1 " "Info: Found entity 1: altsyncram_qsf1" {  } { { "db/altsyncram_qsf1.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/altsyncram_qsf1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qsf1 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|altsyncram_qsf1:FIFOram " "Info: Elaborating entity \"altsyncram_qsf1\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|altsyncram_qsf1:FIFOram\"" {  } { { "db/a_dpfifo_6s81.tdf" "FIFOram" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_gs8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_gs8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_gs8 " "Info: Found entity 1: cmpr_gs8" {  } { { "db/cmpr_gs8.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cmpr_gs8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_gs8 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cmpr_gs8:almost_full_comparer " "Info: Elaborating entity \"cmpr_gs8\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cmpr_gs8:almost_full_comparer\"" {  } { { "db/a_dpfifo_6s81.tdf" "almost_full_comparer" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 53 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_gs8 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cmpr_gs8:two_comparison " "Info: Elaborating entity \"cmpr_gs8\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cmpr_gs8:two_comparison\"" {  } { { "db/a_dpfifo_6s81.tdf" "two_comparison" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 54 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_tnb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_tnb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_tnb " "Info: Found entity 1: cntr_tnb" {  } { { "db/cntr_tnb.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cntr_tnb.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_tnb DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cntr_tnb:rd_ptr_msb " "Info: Elaborating entity \"cntr_tnb\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cntr_tnb:rd_ptr_msb\"" {  } { { "db/a_dpfifo_6s81.tdf" "rd_ptr_msb" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 55 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ao7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ao7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ao7 " "Info: Found entity 1: cntr_ao7" {  } { { "db/cntr_ao7.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cntr_ao7.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ao7 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cntr_ao7:usedw_counter " "Info: Elaborating entity \"cntr_ao7\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cntr_ao7:usedw_counter\"" {  } { { "db/a_dpfifo_6s81.tdf" "usedw_counter" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 56 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_unb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_unb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_unb " "Info: Found entity 1: cntr_unb" {  } { { "db/cntr_unb.tdf" "" { Text "G:/FPGA/DE2_115_ADA/db/cntr_unb.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_unb DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cntr_unb:wr_ptr " "Info: Elaborating entity \"cntr_unb\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|scfifo:\\normal_fifo:fifo_eab_on:in_fifo\|scfifo_dhh1:auto_generated\|a_dpfifo_6s81:dpfifo\|cntr_unb:wr_ptr\"" {  } { { "db/a_dpfifo_6s81.tdf" "wr_ptr" { Text "G:/FPGA/DE2_115_ADA/db/a_dpfifo_6s81.tdf" 57 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/auk_dspip_avalon_streaming_source_fir_101.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fir_compiler-library/auk_dspip_avalon_streaming_source_fir_101.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source_fir_101-rtl " "Info: Found design unit 1: auk_dspip_avalon_streaming_source_fir_101-rtl" {  } { { "auk_dspip_avalon_streaming_source_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_source_fir_101.vhd" 92 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source_fir_101 " "Info: Found entity 1: auk_dspip_avalon_streaming_source_fir_101" {  } { { "auk_dspip_avalon_streaming_source_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_source_fir_101.vhd" 59 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source_fir_101 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source " "Info: Elaborating entity \"auk_dspip_avalon_streaming_source_fir_101\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\"" {  } { { "filter_ast.vhd" "source" { Text "G:/FPGA/DE2_115_ADA/filter_ast.vhd" 110 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/auk_dspip_avalon_streaming_controller_fir_101.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fir_compiler-library/auk_dspip_avalon_streaming_controller_fir_101.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller_fir_101-struct " "Info: Found design unit 1: auk_dspip_avalon_streaming_controller_fir_101-struct" {  } { { "auk_dspip_avalon_streaming_controller_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_controller_fir_101.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller_fir_101 " "Info: Found entity 1: auk_dspip_avalon_streaming_controller_fir_101" {  } { { "auk_dspip_avalon_streaming_controller_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_controller_fir_101.vhd" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller_fir_101 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl " "Info: Elaborating entity \"auk_dspip_avalon_streaming_controller_fir_101\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl\"" {  } { { "filter_ast.vhd" "intf_ctrl" { Text "G:/FPGA/DE2_115_ADA/filter_ast.vhd" 127 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "filter_st DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore " "Info: Elaborating entity \"filter_st\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\"" {  } { { "filter_ast.vhd" "fircore" { Text "G:/FPGA/DE2_115_ADA/filter_ast.vhd" 142 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/tdl_da_lc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir_compiler-library/tdl_da_lc.v" { { "Info" "ISGN_ENTITY_NAME" "1 tdl_da_lc " "Info: Found entity 1: tdl_da_lc" {  } { { "tdl_da_lc.v" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/tdl_da_lc.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tdl_da_lc DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|tdl_da_lc:Utdldalc0n " "Info: Elaborating entity \"tdl_da_lc\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|tdl_da_lc:Utdldalc0n\"" {  } { { "filter_st.v" "Utdldalc0n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 100 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/sadd_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir_compiler-library/sadd_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sadd_cen " "Info: Found entity 1: sadd_cen" {  } { { "sadd_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/sadd_cen.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_cen:U_0_sym_add " "Info: Elaborating entity \"sadd_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_cen:U_0_sym_add\"" {  } { { "filter_st.v" "U_0_sym_add" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 179 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/rom_lut_r_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir_compiler-library/rom_lut_r_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_lut_r_cen " "Info: Found entity 1: rom_lut_r_cen" {  } { { "rom_lut_r_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/rom_lut_r_cen.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur0_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur0_n_0_pp\"" {  } { { "filter_st.v" "Ur0_n_0_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 257 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur0_n_13_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur0_n_13_pp\"" {  } { { "filter_st.v" "Ur0_n_13_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 504 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur1_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur1_n_0_pp\"" {  } { { "filter_st.v" "Ur1_n_0_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 523 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur1_n_13_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur1_n_13_pp\"" {  } { { "filter_st.v" "Ur1_n_13_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 770 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur2_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur2_n_0_pp\"" {  } { { "filter_st.v" "Ur2_n_0_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 789 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur2_n_13_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur2_n_13_pp\"" {  } { { "filter_st.v" "Ur2_n_13_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1036 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur3_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur3_n_0_pp\"" {  } { { "filter_st.v" "Ur3_n_0_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1055 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur3_n_13_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur3_n_13_pp\"" {  } { { "filter_st.v" "Ur3_n_13_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1302 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur4_n_0_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur4_n_0_pp\"" {  } { { "filter_st.v" "Ur4_n_0_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1321 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_lut_r_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur4_n_13_pp " "Info: Elaborating entity \"rom_lut_r_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|rom_lut_r_cen:Ur4_n_13_pp\"" {  } { { "filter_st.v" "Ur4_n_13_pp" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1568 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/sadd_lpm_cen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir_compiler-library/sadd_lpm_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sadd_lpm_cen " "Info: Found entity 1: sadd_lpm_cen" {  } { { "sadd_lpm_cen.v" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/sadd_lpm_cen.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n\"" {  } { { "filter_st.v" "Uadd_0_lut_l_0_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1619 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n\"" {  } { { "filter_st.v" "Uadd_0_lut_l_1_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1648 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n\"" {  } { { "filter_st.v" "Uadd_0_lut_l_2_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1665 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n\"" {  } { { "filter_st.v" "Uadd_0_lut_l_3_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 1674 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n\"" {  } { { "filter_st.v" "Uadd_cen_l_0_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 2061 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\"" {  } { { "filter_st.v" "Uadd_cen_l_1_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 2074 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sadd_lpm_cen DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_2_n_0_n " "Info: Elaborating entity \"sadd_lpm_cen\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_2_n_0_n\"" {  } { { "filter_st.v" "Uadd_cen_l_2_n_0_n" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 2083 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/mac_tl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir_compiler-library/mac_tl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_tl " "Info: Found entity 1: mac_tl" {  } { { "mac_tl.v" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/mac_tl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_tl DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|mac_tl:Umtl " "Info: Elaborating entity \"mac_tl\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|mac_tl:Umtl\"" {  } { { "filter_st.v" "Umtl" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 2092 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir_compiler-library/par_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fir_compiler-library/par_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 par_ctrl " "Info: Found entity 1: par_ctrl" {  } { { "par_ctrl.v" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/par_ctrl.v" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "par_ctrl DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|par_ctrl:Uctrl " "Info: Elaborating entity \"par_ctrl\" for hierarchy \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|par_ctrl:Uctrl\"" {  } { { "filter_st.v" "Uctrl" { Text "G:/FPGA/DE2_115_ADA/filter_st.v" 2114 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "DE2_115_ADDA_TOP:U1\|sin_out\[13\] " "Warning (12110): Net \"DE2_115_ADDA_TOP:U1\|sin_out\[13\]\" is missing source, defaulting to GND" {  } { { "DE2_115_ADDA_TOP.v" "sin_out\[13\]" { Text "G:/FPGA/DE2_115_ADA/DE2_115_ADDA_TOP.v" 66 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "" 0 -1}  } {  } 0 0 "Net is missing source, defaulting to GND" 0 0 "" 0 -1}
{ "Warning" "WSGN_USE_OPENCORE_PLUS" "" "Warning: OpenCore Plus Hardware Evaluation feature is turned on for the following cores" { { "Warning" "WSGN_FOUND_OCP_CORE" "FIR_Compiler (6AF7_0012) " "Warning: \"FIR_Compiler (6AF7_0012)\" will use the OpenCore Plus Hardware Evaluation feature" {  } {  } 0 0 "\"%1!s!\" will use the OpenCore Plus Hardware Evaluation feature" 0 0 "" 0 -1} { "Warning" "WSGN_FOUND_OCP_CORE" "\"NCO\" (6AF7_0014) " "Warning: \"\"NCO\" (6AF7_0014)\" will use the OpenCore Plus Hardware Evaluation feature" {  } {  } 0 0 "\"%1!s!\" will use the OpenCore Plus Hardware Evaluation feature" 0 0 "" 0 -1}  } {  } 0 0 "OpenCore Plus Hardware Evaluation feature is turned on for the following cores" 0 0 "" 0 -1}
{ "Warning" "WSCI_OPENCORE_USER_MSG_ROOT" "" "Warning: Messages from megafunction that supports OpenCore Plus feature" { { "Warning" "WSCI_OPENCORE_USER_MSG_CORE_ROOT" "NCO MegaCore " "Warning: Messages from megafunction that supports OpenCore Plus feature NCO MegaCore" { { "Warning" "WSCI_OPENCORE_USER_MSG_SUB" "The output signals fsin_o and fcos_o are forced low when the evaluation time expires " "Warning: The output signals fsin_o and fcos_o are forced low when the evaluation time expires" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Messages from megafunction that supports OpenCore Plus feature %1!s!" 0 0 "" 0 -1} { "Warning" "WSCI_OPENCORE_USER_MSG_CORE_ROOT" "FIR MegaCore v6.1 " "Warning: Messages from megafunction that supports OpenCore Plus feature FIR MegaCore v6.1" { { "Warning" "WSCI_OPENCORE_USER_MSG_SUB" "The output signal datao will go low when the evaluation time expires " "Warning: The output signal datao will go low when the evaluation time expires" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSCI_OPENCORE_USER_MSG_SUB" "The output signals data_out will go low when the evaluation time expires " "Warning: The output signals data_out will go low when the evaluation time expires" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Messages from megafunction that supports OpenCore Plus feature %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Messages from megafunction that supports OpenCore Plus feature" 0 0 "" 0 -1}
{ "Warning" "WSCI_OPENCORE_HARD_TIMEOUT_INFO" "1 hour " "Warning: Megafunction that supports OpenCore Plus feature will stop functioning in 1 hour after device is programmed" {  } {  } 0 0 "Megafunction that supports OpenCore Plus feature will stop functioning in %1!s! after device is programmed" 0 0 "" 0 -1}
{ "Info" "ISCI_OPENCORE_SOFT_TIMEOUT_INF_INFO" "" "Info: Evaluation period of megafunction that supports OpenCore Plus feature can be extended indefinitely by using tethered operation" {  } {  } 0 0 "Evaluation period of megafunction that supports OpenCore Plus feature can be extended indefinitely by using tethered operation" 0 0 "" 0 -1}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "Warning: 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 0 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "Warning: The following bidir pins have no drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "I2C_SDAT " "Warning: Bidir \"I2C_SDAT\" has no driver" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 89 -1 0 } }  } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1}  } {  } 0 0 "The following bidir pins have no drivers" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "I2C_SCLK GND " "Warning (13410): Pin \"I2C_SCLK\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 88 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ADC_OEB_A GND " "Warning (13410): Pin \"ADC_OEB_A\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 96 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ADC_OEB_B GND " "Warning (13410): Pin \"ADC_OEB_B\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 97 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DAC_DA\[13\] GND " "Warning (13410): Pin \"DAC_DA\[13\]\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 102 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DAC_DB\[13\] GND " "Warning (13410): Pin \"DAC_DB\[13\]\" is stuck at GND" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 103 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DAC_MODE VCC " "Warning (13410): Pin \"DAC_MODE\" is stuck at VCC" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 104 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Info: Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "IFTM_FTM_INSERTED_LCELL_TO_HONOR_MAX_FANOUT" "6 DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl\|stall_reg " "Info: Inserted 6 logic cells for Maximum Fan-Out assignment on \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_controller_fir_101:intf_ctrl\|stall_reg\"" {  } { { "auk_dspip_avalon_streaming_controller_fir_101.vhd" "" { Text "G:/FPGA/DE2_115_ADA/fir_compiler-library/auk_dspip_avalon_streaming_controller_fir_101.vhd" 73 -1 0 } }  } 0 0 "Inserted %1!d! logic cells for Maximum Fan-Out assignment on \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "33 33 " "Info: 33 registers lost all their fanouts during netlist optimizations. The first 33 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|at_sink_sop_int " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|at_sink_sop_int\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|at_sink_eop_int " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|at_sink_eop_int\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[3\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[2\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[1\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[0\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|mynco:sin1\|mynco_st:mynco_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_ori:auto_generated\|counter_reg_bit\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_1_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_1_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_2_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_2_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_1_n\|pipe\[0\]\[35\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_1_n\|pipe\[0\]\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_1_n\|pipe\[0\]\[36\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_1_n\|pipe\[0\]\[36\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_2_n\|pipe\[0\]\[35\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_2_n\|pipe\[0\]\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\|pipe\[0\]\[35\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\|pipe\[0\]\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\|pipe\[0\]\[36\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_1_n_0_n\|pipe\[0\]\[36\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_4_lut_l_3_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_1_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_1_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_1_n\|pipe\[0\]\[35\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_1_n\|pipe\[0\]\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n\|pipe\[0\]\[35\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_cen_l_0_n_0_n\|pipe\[0\]\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_3_lut_l_3_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_3_lut_l_3_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_1_lut_l_3_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_1_lut_l_3_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n\|pipe\[0\]\[34\] " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|filter_st:fircore\|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n\|pipe\[0\]\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.start " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.start\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.sop " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.sop\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.run1 " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.run1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.st_err " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.st_err\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.end1 " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_source_fir_101:source\|source_state.end1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_state.start " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_state.start\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_state.stall " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_state.stall\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_state.st_err " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_state.st_err\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_out_state.normal " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_out_state.normal\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_out_state.empty_and_ready " "Info: Register \"DE2_115_ADDA_TOP:U1\|filter:filt\|filter_ast:filter_ast_inst\|auk_dspip_avalon_streaming_sink_fir_101:sink\|sink_out_state.empty_and_ready\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "pzdyqx:nabboc " "Info: Timing-Driven Synthesis is running on partition \"pzdyqx:nabboc\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll " "Info: Adding node \"DE2_115_ADDA_TOP:U1\|pll:pll_100\|altpll:altpll_component\|pll\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "34 " "Warning: Design contains 34 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK2_50 " "Warning (15610): No output dependent on input pin \"CLOCK2_50\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 84 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK3_50 " "Warning (15610): No output dependent on input pin \"CLOCK3_50\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 85 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[0\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[0\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[1\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[1\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[2\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[2\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[3\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[3\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[4\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[4\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[5\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[5\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[6\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[6\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[7\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[7\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[8\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[8\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[9\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[9\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[10\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[10\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[11\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[11\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[12\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[12\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DA\[13\] " "Warning (15610): No output dependent on input pin \"ADC_DA\[13\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 94 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[0\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[0\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[1\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[1\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[2\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[2\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[3\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[3\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[4\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[4\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[5\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[5\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[6\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[6\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[7\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[7\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[8\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[8\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[9\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[9\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[10\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[10\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[11\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[11\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[12\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[12\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_DB\[13\] " "Warning (15610): No output dependent on input pin \"ADC_DB\[13\]\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 95 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_OTR_A " "Warning (15610): No output dependent on input pin \"ADC_OTR_A\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 98 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "ADC_OTR_B " "Warning (15610): No output dependent on input pin \"ADC_OTR_B\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 99 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "OSC_SMA_ADC4 " "Warning (15610): No output dependent on input pin \"OSC_SMA_ADC4\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 107 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SMA_DAC4 " "Warning (15610): No output dependent on input pin \"SMA_DAC4\"" {  } { { "de2_115_adda.v" "" { Text "G:/FPGA/DE2_115_ADA/de2_115_adda.v" 108 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4205 " "Info: Implemented 4205 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "38 " "Info: Implemented 38 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Info: Implemented 39 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "4069 " "Info: Implemented 4069 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "52 " "Info: Implemented 52 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 64 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 64 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "279 " "Info: Peak virtual memory: 279 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 17 21:12:59 2011 " "Info: Processing ended: Fri Jun 17 21:12:59 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:43 " "Info: Elapsed time: 00:00:43" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:36 " "Info: Total CPU time (on all processors): 00:00:36" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
